Logic Gate Diagram Builder

Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.

Expression

Boolean expression

Accepts + · ' ¬ ∧ ∨ ⊕ ~ ! & | and the words AND, OR, NOT, XOR.

read as ((A · B) + (A · ¬C))

Notation used on this page

Positive logic: 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
Operators: · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
Precedence, highest first: ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
Truth-table row order: Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
Minterms and maxterms: Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
Symbol standards: IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
Symbol-set toggle: Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.

This is one correct circuit for the expression, not the only one. The notes below name every choice the drawing made that a different tool would make differently.

Distinctive shape — ANSI/IEEE Std 91-1984Rectangular shape — IEC 60617-12 (constructed metrics)IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.

Gate list for Y: every gate, its inputs and the expression it carries
Type	Inputs	Output expression
AND	A, B	A · B
NOT	C	C′
AND	A, g1	A · C′
OR	g0, g2	A · B + A · C′

Circuit description and netlist

Logic gate schematic. 3 inputs: A, B and C. 4 gates: 2 AND, 1 OR and 1 NOT. The output Y is driven by an OR gate. The longest signal path passes through 3 gates. 1 junction dot marks where a signal fans out to more than one gate.

The circuit computes Y = A · B + A · C′, read as ((A · B) + (A · ¬C)).

Netlist for Y: every gate, its inputs and the expression it carries
Gate	Type	Inputs	Output expression
g0	AND	A, B	A · B
g1	NOT	C	C′
g2	AND	A, g1	A · C′
g3	OR	g0, g2	A · B + A · C′

View as a truth table

How an expression becomes a schematic

The expression is parsed into a tree, each operator node becomes a gate, and each variable becomes a primary input. Shared sub-expressions become one gate with fan-out rather than two copies, which is why the gate count under the drawing is usually lower than the number of operators you typed.

Two readings are printed beside the field: what you wrote, and the fully parenthesised reading the parser used. Precedence is not universal between textbooks, so a tool that shows an answer without showing which question it answered teaches something false.

Both symbol standards, chosen before the first frame

Every diagram on this site ships in both ANSI/IEEE Std 91-1984 distinctive shapes and IEC 60617-12 rectangular symbols, in the same markup and over the same layout. The toggle in the header picks one in CSS, before the page paints, so the choice costs no reflow and no flash — and the standard you hand in is the standard your course marks against.

Both drawings are generated from one layout, so switching re-skins the symbols and cannot move a wire.

Gate count and circuit depth

Two depth numbers are printed, not one. Textbooks disagree about whether an input inverter counts as a logic level, so the tool gives the count both ways and names the convention rather than picking one silently. The gate-input count is the third measure — it is what a two-level cost model actually charges for.

This is one correct circuit, not the only one

Any expression has many equally correct schematics: the operand order inside a commutative gate, whether a wide AND is drawn as one gate or as a tree of two-input gates, and which shared node is drawn as fan-out are all choices. The notes under the diagram name every choice this drawing made that a different, equally correct tool would make differently.

Junction dots follow the IEEE Std 315-1975 convention: a dot at a crossing means connected, no dot means not connected. Four-way dotted junctions are avoided by staggering into two T-junctions.

Start from a worked example

Worked examples

Sources

C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)
IEEE Std 315-1975, Graphic Symbols for Electrical and Electronics Diagrams (withdrawn 2019) — the junction-dot convention.
Texas Instruments, Overview of IEEE Standard 91-1984: Explanation of Logic Symbols, SDYZ001A.