A·B·C·D + Ā·B̄·C̄·D̄ — logic gate diagram
exam standard11 two-input primitives, or 3 wide gates plus 4 inverters
Answer
7 gates, 4 inputs; output column 1000000000000001
Why this example is worth doing
Two four-input AND gates feeding an OR, with four inverters on the second AND's inputs. It is here for the fan-in question: a four-input AND is one symbol on paper but in a real library it may be a tree of two-input gates with twice the delay. The builder exposes a maximum fan-in setting and redraws the network as a tree when the limit is exceeded, which is the point at which a schematic stops being a picture of the algebra and starts being a picture of the hardware.
Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.
How the answer is reached
Netlist
| Node | Gate | Inputs |
|---|---|---|
| g0 | and | i0, i1, i2, i3 |
| g1 | not | i0 |
| g2 | not | i1 |
| g3 | not | i2 |
| g4 | not | i3 |
| g5 | and | g1, g2, g3, g4 |
| g6 | or | g0, g5 |
Truth table
| # | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 2 | 0 | 0 | 1 | 0 | 0 |
| 3 | 0 | 0 | 1 | 1 | 0 |
| 4 | 0 | 1 | 0 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 | 0 |
| 6 | 0 | 1 | 1 | 0 | 0 |
| 7 | 0 | 1 | 1 | 1 | 0 |
| 8 | 1 | 0 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 | 0 |
| 10 | 1 | 0 | 1 | 0 | 0 |
| 11 | 1 | 0 | 1 | 1 | 0 |
| 12 | 1 | 1 | 0 | 0 | 0 |
| 13 | 1 | 1 | 0 | 1 | 0 |
| 14 | 1 | 1 | 1 | 0 | 0 |
| 15 | 1 | 1 | 1 | 1 | 1 |