(A + B̄)·(B + C̄)·(C + Ā) — logic gate diagram

edge case8 primitives: 3 ORs, 3 inverters, 2 ANDs; cyclic structure

Answer

7 gates, 3 inputs; output column 10000001

Why this example is worth doing

Three OR gates feeding an AND, wired in a cycle so that each variable appears once true and once complemented. It is deliberately the least symmetric-looking diagram in the set, and it exists to test the layout engine rather than the reader: wires cross, and the router has to place junction dots and choose crossing points deterministically so that the same input always yields the same picture. Stable layout is what makes a diagram safe to paste into a lab report.

Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.

How the answer is reached

Netlist

Netlist — columns Node, Gate, Inputs
NodeGateInputs
g0noti1
g1ori0, g0
g2noti2
g3ori1, g2
g4noti0
g5ori2, g4
g6andg1, g3, g5

Truth table

Truth table — columns #, A, B, C, F
#ABCF
00001
10010
20100
30110
41000
51010
61100
71111

Compare with

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The field arrives filled in with this example’s input.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements