A ⊕ B ⊕ C — logic gate diagram
core2 XOR gates chained
Answer
1 gates, 3 inputs; output column 01101001
Why this example is worth doing
A three-input XOR drawn as a chain of two two-input gates, because three-input XOR is not a standard physical part. This is the first diagram whose structure is a choice rather than a transcription: the same function can be drawn as a chain, which is cheap and has two gate delays, or as a balanced tree, which matters once there are eight inputs. The page shows both and gives the depth formula, connecting the drawing to the propagation-delay question that follows it in most courses.
Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.
How the answer is reached
Netlist
| Node | Gate | Inputs |
|---|---|---|
| g0 | xor | i0, i1, i2 |
Truth table
| # | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 1 |