Digital Logic Toolkit — Multiplexers & decoders
Multiplexers and decoders: 2:1, 4:1, 8:1 mux and 2:4, 3:8 decoders
Multiplexers from 2:1 to 16:1 and decoders from 2:4 to 4:16, with the selection logic derived.
Conventions on this page
- Select-line numbering
- Select inputs are S₀ … S₍ₖ₋₁₎ with S₀ the least significant bit, so the selected index is the sum of Sᵢ·2ⁱ. On a 4:1 mux S₁S₀ = 10 selects I₂; on an 8:1 mux S₂S₁S₀ = 101 selects I₅.
- The A/B/C trap
- Many textbooks and most datasheets label the same pins A, B and C with A as the LSB. The ordering is what matters, not the letters, and reading them the other way round is the most common wiring error with these parts.
- Data-input numbering
- Iₖ is routed to the output when the select value equals k. Decoder output Yₖ is the one asserted when the select value equals k.
- Enable
- The default here is an active-HIGH EN, with a switch for the active-LOW EN_n that most real parts use. A trailing _n means the pin is asserted LOW; on a schematic it is drawn as an overbar or a bubble.
- Output polarity
- The default decoder has active-HIGH outputs, so exactly one output is 1. The switch selects active-LOW outputs, so exactly one output is 0 — which is what a 74HC138 or 74HC139 actually produces. Every table and every equation is recomputed under the switch.
- Operator glyphs
- · is AND, + is OR, a prime is NOT. Precedence runs, tightest first: parentheses, NOT, AND, XOR/XNOR, NAND/NOR, OR.
Set the pins, read the output
Y = 1
S₁S₀ = 10 → index 2 → Y = I₂ = 1.
- Y = EN · (S₁′ · S₀′ · I₀ + S₁′ · S₀ · I₁ + S₁ · S₀′ · I₂ + S₁ · S₀ · I₃)
Every device, in full
2:1 multiplexer
| EN | S₀ | Y |
|---|---|---|
| 0 | X | 0 |
| 1 | 0 | I₀ |
| 1 | 1 | I₁ |
- Y = EN · (S₀′ · I₀ + S₀ · I₁)
Gate-level: 1 inverter, 2 three-input ANDs (the third input is the enable), 1 OR.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 4 inputs: EN, S0, I0 and I1. 5 gates: 3 AND, 1 OR and 1 NOT. The output Y is driven by an AND gate. The longest signal path passes through 4 gates. 1 junction dot marks where a signal fans out to more than one gate.
The drawing was read back as an expression and matched the one above on every input combination.
Full truth table for the 2:1 multiplexer, every input column
| EN | S₀ | I₀ | I₁ | Y |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |
4:1 multiplexer
| EN | S₁ | S₀ | Y |
|---|---|---|---|
| 0 | X | X | 0 |
| 1 | 0 | 0 | I₀ |
| 1 | 0 | 1 | I₁ |
| 1 | 1 | 0 | I₂ |
| 1 | 1 | 1 | I₃ |
- Y = EN · (S₁′ · S₀′ · I₀ + S₁′ · S₀ · I₁ + S₁ · S₀′ · I₂ + S₁ · S₀ · I₃)
Gate-level: 2 inverters, 4 four-input ANDs, 1 four-input OR.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 7 inputs: EN, I0, S0, I1, S1, I2 and I3. 8 gates: 5 AND, 1 OR and 2 NOT. The output Y is driven by an AND gate. The longest signal path passes through 4 gates. 6 junction dots mark where a signal fans out to more than one gate.
The drawing was read back as an expression and matched the one above on every input combination.
8:1 multiplexer
| EN | S₂ | S₁ | S₀ | Y |
|---|---|---|---|---|
| 0 | X | X | X | 0 |
| 1 | 0 | 0 | 0 | I₀ |
| 1 | 0 | 0 | 1 | I₁ |
| 1 | 0 | 1 | 0 | I₂ |
| 1 | 0 | 1 | 1 | I₃ |
| 1 | 1 | 0 | 0 | I₄ |
| 1 | 1 | 0 | 1 | I₅ |
| 1 | 1 | 1 | 0 | I₆ |
| 1 | 1 | 1 | 1 | I₇ |
- Y = EN · (S₂′ · S₁′ · S₀′ · I₀ + S₂′ · S₁′ · S₀ · I₁ + S₂′ · S₁ · S₀′ · I₂ + S₂′ · S₁ · S₀ · I₃ + S₂ · S₁′ · S₀′ · I₄ + S₂ · S₁′ · S₀ · I₅ + S₂ · S₁ · S₀′ · I₆ + S₂ · S₁ · S₀ · I₇)
Gate-level: 3 inverters, 8 five-input ANDs, 1 eight-input OR.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 12 inputs: EN, I0, I1, I2, S1, S0, I3, I4, S2, I7, I5 and I6. 15 gates: 9 AND, 3 OR and 3 NOT. The output Y is driven by an AND gate. The longest signal path passes through 5 gates. 21 junction dots mark where a signal fans out to more than one gate.
The drawing was read back as an expression and matched the one above on every input combination.
2:4 decoder
| EN | S₁ | S₀ | Y₃ | Y₂ | Y₁ | Y₀ |
|---|---|---|---|---|---|---|
| 0 | X | X | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |
- Y₀ = EN · S₁′ · S₀′
- Y₁ = EN · S₁′ · S₀
- Y₂ = EN · S₁ · S₀′
- Y₃ = EN · S₁ · S₀
Gate-level: 2 inverters and 4 three-input ANDs — one AND per minterm, plus the enable.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 3 inputs: EN, S1 and S0. 3 gates: 1 AND and 2 NOT. The output Y0 is driven by an AND gate. The longest signal path passes through 2 gates.
The drawing was read back as an expression and matched the one above on every input combination.
Checked over every select value: exactly one output is asserted when the part is enabled, and none when it is not. That is the one-hot property, and it is why decoders drive chip-selects and tri-state enables.
Full truth table for the 2:4 decoder, every input column
| EN | S₁ | S₀ | Y₃ | Y₂ | Y₁ | Y₀ |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |
3:8 decoder
| EN | S₂ | S₁ | S₀ | Y₇ | Y₆ | Y₅ | Y₄ | Y₃ | Y₂ | Y₁ | Y₀ |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | X | X | X | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
- Y₀ = EN · S₂′ · S₁′ · S₀′
- Y₁ = EN · S₂′ · S₁′ · S₀
- Y₂ = EN · S₂′ · S₁ · S₀′
- Y₃ = EN · S₂′ · S₁ · S₀
- Y₄ = EN · S₂ · S₁′ · S₀′
- Y₅ = EN · S₂ · S₁′ · S₀
- Y₆ = EN · S₂ · S₁ · S₀′
- Y₇ = EN · S₂ · S₁ · S₀
Gate-level: 3 inverters and 8 four-input ANDs — one AND per minterm, plus the enable.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 4 inputs: EN, S2, S1 and S0. 4 gates: 1 AND and 3 NOT. The output Y0 is driven by an AND gate. The longest signal path passes through 2 gates.
The drawing was read back as an expression and matched the one above on every input combination.
Checked over every select value: exactly one output is asserted when the part is enabled, and none when it is not. That is the one-hot property, and it is why decoders drive chip-selects and tri-state enables.
What a multiplexer does
A multiplexer has n data inputs, k = log₂n select inputs and one output. The select value is a number, and the output is whichever data input carries that number. It is a rotary switch you turn with a binary code — with two caveats that matter as soon as you build something. A logic mux is not bidirectional: data flows from the inputs to the output and nowhere else, unlike an analogue switch such as the 4051, which passes signals both ways. And it is a logic element: the output is a regenerated 0 or 1, not the input voltage.
The reverse device is the demultiplexer: one input, one select value, and the data appears on exactly one of n outputs.
The select-line convention, and the error it prevents
S₀ is the least significant bit, so the selected index is Σ Sᵢ·2ⁱ. Written most-significant-first — the way it is printed everywhere on this page — S₁S₀ = 10 is binary 2 and routes I₂, and S₂S₁S₀ = 101 is binary 5 and routes I₅.
The compressed tables above do not assert that mapping. For each select value the engine drives one data input high at a time and asks the expression which one reaches the output; the answer is the number in the table. So a convention stated in prose and a table generated from the expression cannot drift apart.
A, B, C is the same convention with different letters
The 74HC151 calls its select pins A, B and C, with A as the least significant. A textbook that writes them in the order C B A is writing the most significant first, exactly like S₂S₁S₀. Nothing about the device changes; only the label does. Wire A to the top bit of your address and every routing decision is mirrored.What a decoder does
A decoder has n select (address) inputs and 2ⁿ outputs, and asserts exactly the one whose index equals the select value. With the part enabled, exactly one output is asserted and every other output sits at its inactive level — a one-hot code. That property is checked above for both decoders over every select value, and it is the reason decoders drive memory chip-selects and tri-state enables: it is the cheapest hardware guarantee that two drivers are never on at once.
Enable inputs
What enable does on a multiplexer
With EN = 0 the output is forced to 0 — Y = EN · Σ …, so the whole sum is gated. Toggle the enable in the tool above with any data pattern you like and the output does not move.
Real parts are not unanimous about this. The 74HC151’s active-low Ē forces Y LOW and its complementary output Ȳ HIGH, exactly as modelled here. A bus multiplexer such as the 74HC257 instead goes to high impedance when disabled, which is a third state and not a logic level at all. Read the datasheet rather than assuming; a disabled mux driving a wired bus and a disabled mux driving 0 behave completely differently.
What enable does on a decoder
With the part disabled, all outputs go to their inactive level: 0 for active-high outputs, 1 for active-low outputs. No output is selected at all, which is a state the select lines alone cannot produce.
Why enables let you cascade
That is exactly what makes decoders composable. Feed S₁S₀ to two 2:4 decoders, drive the first’s enable with EN·S₂′ and the second’s with EN·S₂, and the pair is a 3:8 decoder — with an active-high EN tied to 1 that is one inverter and nothing else. The same trick stacked once more makes a 4:16 from two 3:8s.
Active-low enables and outputs on real parts
The 74HC138 has three enables: Ē1 and Ē2 active-low, E3 active-high. The part is enabled only when Ē1 = 0, Ē2 = 0 and E3 = 1. That is not decoration: it means a 4:16 or 5:32 decoder can be assembled from ’138s with no external gates, because the address bits above the third one drive the enables directly.
Building bigger devices from smaller ones
An 8:1 multiplexer from two 4:1s and one 2:1
EN · (S₂′ · (S₁′ · S₀′ · I₀ + S₁′ · S₀ · I₁ + S₁ · S₀′ · I₂ + S₁ · S₀ · I₃) + S₂ · (S₁′ · S₀′ · I₄ + S₁′ · S₀ · I₅ + S₁ · S₀′ · I₆ + S₁ · S₀ · I₇))
Split the data inputs in half, let each 4:1 handle its half using S₁S₀, and let a 2:1 driven by S₂ choose between the two results. That decomposition is Shannon expansion on S₂, and the engine confirms it: this expression and the direct 8:1 expression agree on every one of the 4,096 combinations of the enable, three selects and eight data inputs.
A 3:8 decoder from two 2:4s
| S₂S₁S₀ | Decoder enabled | Its local select | Global output asserted |
|---|---|---|---|
| 000 | first (enabled by EN·S₂′) | 00 | Y₀ |
| 001 | first (enabled by EN·S₂′) | 01 | Y₁ |
| 010 | first (enabled by EN·S₂′) | 10 | Y₂ |
| 011 | first (enabled by EN·S₂′) | 11 | Y₃ |
| 100 | second (enabled by EN·S₂) | 00 | Y₄ |
| 101 | second (enabled by EN·S₂) | 01 | Y₅ |
| 110 | second (enabled by EN·S₂) | 10 | Y₆ |
| 111 | second (enabled by EN·S₂) | 11 | Y₇ |
Exactly one output is asserted in all eight cases, and the numbering comes out in order: the pair is a 3:8 decoder. Remove the enable and neither half responds, which is the state a plain three-input AND array cannot reach.
Decoder outputs are minterms
The outputs of an n-to-2ⁿ decoder are the 2ⁿ minterms of its select inputs. Read the algebra above: Y₀ = EN·S₁′·S₀′ is m₀, Y₃ = EN·S₁·S₀ is m₃. So a decoder plus one OR gate implements any Boolean function of n variables straight from its minterm list, with no minimisation at all.
Worked on the full adder, with A → S₂, B → S₁, Cᵢₙ → S₀: the sum is Σm(1, 2, 4, 7), so OR together Y₁, Y₂, Y₄, Y₇; the carry-out is Σm(3, 5, 6, 7), so OR together Y₃, Y₅, Y₆, Y₇. Two four-input OR gates, and the engine confirms both: each OR of decoder outputs is equivalent to the adder function it is supposed to be, over all eight rows.
With active-low outputs, use a NAND
A 74HC138 asserts its selected output LOW, so the outputs you want to OR are already complemented. Feed the same four wires into a four-input NAND instead: (Y_a′ · Y_b′ · Y_c′ · Y_d′)′ = Y_a + Y_b + Y_c + Y_d by De Morgan. Checked here the same way — it agrees on all eight rows.Implementing any function with a multiplexer
Worked on one function, both ways, so the trade is visible: F(A, B, C) = Σm(1, 2, 4, 7), which in canonical sum-of-products is A′ · B′ · C + A′ · B · C′ + A · B′ · C′ + A · B · C.
Method A — full decode on an 8:1 mux
Wire the variables to the selects — A → S₂, B → S₁, C → S₀ — and tie each data input to the function’s value at that minterm. No gates at all.
- I₀ = 0
- I₁ = 1
- I₂ = 1
- I₃ = 0
- I₄ = 1
- I₅ = 0
- I₆ = 0
- I₇ = 1
Method B — Shannon expansion onto a 4:1 mux
Use the top two variables as selects and let the third arrive as data. For each value of A B the function reduces to a residue in C alone, and a residue of one variable can only be 0, 1, C or C′. Each residue below was produced by fixing the select variables and evaluating what was left.
| A B | covers | F on those rows | data input | residue |
|---|---|---|---|---|
| 00 | m0, m1 | 0, 1 | I₀ | C |
| 01 | m2, m3 | 1, 0 | I₁ | C′ |
| 10 | m4, m5 | 1, 0 | I₂ | C′ |
| 11 | m6, m7 | 0, 1 | I₃ | C |
A 4:1 mux and one inverter — for the two inputs that need C′ — implement the same function. The general statement is Shannon (Boole) expansion: f(A, B, C) = A′·f(0, B, C) + A·f(1, B, C), applied once per select variable.
| A B C | F | Method A output | Method B output |
|---|---|---|---|
| 000 | 0 | 0 | 0 |
| 001 | 1 | 1 | 1 |
| 010 | 1 | 1 | 1 |
| 011 | 0 | 0 | 0 |
| 100 | 1 | 1 | 1 |
| 101 | 0 | 0 | 0 |
| 110 | 0 | 0 | 0 |
| 111 | 1 | 1 | 1 |
Both agree with F on all eight rows. The choice between them is size against gate count: Method A needs a mux twice as large and nothing else; Method B halves the mux and buys at most one inverter.
Demultiplexers
A 1:4 demultiplexer is a 2:4 decoder with the data line driven into the enable input: Y_k = D · m_k(S₁, S₀). There is no second circuit and no second set of tables — it is the same silicon read differently, which is why the 74HC138’s datasheet calls the part a “decoder/demultiplexer”.
| S₁S₀ | Y₃ | Y₂ | Y₁ | Y₀ |
|---|---|---|---|---|
| 00 | 0 | 0 | 0 | D |
| 01 | 0 | 0 | D | 0 |
| 10 | 0 | D | 0 | 0 |
| 11 | D | 0 | 0 | 0 |
Each cell was found by evaluating the output at both values of D: a cell reading D is one that follows the data line, and every other output is 0 regardless. Exactly one output follows D for each select value.
Real parts
74HC157 — quad 2:1 mux, one shared select. 74HC153 — dual 4:1 mux with shared selects and separate enables. 74HC151 — 8:1 mux with both Y and Ȳ and an active-low enable. 74HC139 — dual 2:4 decoder, active-low enable and active-low outputs. 74HC138 — 3:8 decoder, three enables and active-low outputs. 74HC154 — 4:16 decoder.
The pattern worth carrying away: on real parts the enables and the outputs are usually active-LOW, because bipolar logic sank current better than it sourced it and the convention outlived the technology. The tool above defaults to active-HIGH because that is what textbooks teach, and switches to the datasheet convention on demand.
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Start from a worked example
Worked examples
- 2:1 mux, S = 0introthe selector equation
- 4:1 mux, S₁S₀ = 10introselect lines read as a binary index
- 8:1 mux implementing F(A,B,C) = Σm(1,2,4,7)corea mux as a lookup table
- 4:1 mux implementing a 3-variable functioncoreShannon expansion in hardware
- 2:4 decoder, A₁A₀ = 11coreone-hot output
- 3:8 decoder building F = Σm(1,2,4,7)examdecoder plus OR as a canonical implementation
- 1:4 demultiplexer routing one input to fourexamthe mux run backwards
- 4:16 decoder from two 3:8 decodersedge casewhy decoders have enable pins
Sources
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)
- M. Karnaugh, “The Map Method for Synthesis of Combinational Logic Circuits,” Transactions of the AIEE, Part I, vol. 72, no. 5, pp. 593–599, 1953.