Digital Logic Toolkit — NOR gate
NOR gate: truth table, symbol and Boolean expression
Truth table, symbol and algebraic form for (A + B)′, the other universal gate.
The NOR gate
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 1 gate: 1 NOR. The output F is driven by a NOR gate. The longest signal path passes through 1 gate.
Output F0
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = (A + B)′
F = (1 + 1)′ = 0
NOR outputs 1 only when every input is 0.
This is row 4 of 4 — minterm m₃ (A B = 11).
Truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 1 | 0 | 0 | |
| 1 | 1 | 0 |
Canonical forms
- Minterms
- Σm(0)
- Maxterms
- ΠM(1, 2, 3)
- Canonical sum of products
- F = A′ · B′
- Canonical product of sums
- F = (A + B′) · (A′ + B) · (A′ + B′)
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 2 variables, 1 of its 4 cells filled with 1 — cells m₀.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
(A + B)′ = A′ · B′
An AND body with bubbles on the inputs only — the “negative-AND” symbol.
| A | B | (A + B)′ | A′ · B′ |
|---|---|---|---|
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 |
The two columns agree on all 4 rows.
NOR from NAND gates only
n1 = NAND(A, A)= A ↑ An2 = NAND(B, B)= B ↑ Bn3 = NAND(n1, n2)= A ↑ A ↑ (B ↑ B)n4 = NAND(n3, n3)= A ↑ A ↑ (B ↑ B) ↑ (A ↑ A ↑ (B ↑ B))
4 NANDs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
NOR from NOR gates only
n1 = NOR(A, B)= A ↓ B
1 NOR1 level1 gate, 1 level. Verified equivalent to the gate over all 4 input combinations.
Cost
4 transistorsTwo PMOS in series and two NMOS in parallel — the mirror image of the NAND.
- 74HC02 — quad 2-input NOR
- 74HC27 — triple 3-input NOR
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the NOR gate does
A NOR gate outputs 1 only when every one of its inputs is 0; on every other row it outputs 0.
Algebraically it is F = (A + B)′, which expands to F = A′ · B′ = A ↓ B. For n inputs, F = (A₁ + A₂ + … + Aₙ)′
- Not associative. (A ↓ B) ↓ C ≠ A ↓ (B ↓ C), for the same reason NAND is not. A 3-input NOR means (A + B + C)′.
- Functionally complete. Every Boolean function can be built from NOR alone.
- Inverter. NOR(A, A) = A′.
NOR gate truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 2 | 1 | 0 | 0 |
| 3 | 1 | 1 | 0 |
| k | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 0 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 0 |
| k | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 2 | 0 | 0 | 1 | 0 | 0 |
| 3 | 0 | 0 | 1 | 1 | 0 |
| 4 | 0 | 1 | 0 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 | 0 |
| 6 | 0 | 1 | 1 | 0 | 0 |
| 7 | 0 | 1 | 1 | 1 | 0 |
| 8 | 1 | 0 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 | 0 |
| 10 | 1 | 0 | 1 | 0 | 0 |
| 11 | 1 | 0 | 1 | 1 | 0 |
| 12 | 1 | 1 | 0 | 0 | 0 |
| 13 | 1 | 1 | 0 | 1 | 0 |
| 14 | 1 | 1 | 1 | 0 | 0 |
| 15 | 1 | 1 | 1 | 1 | 0 |
Boolean expression and canonical forms
At 2 inputs the function is F = (A + B)′, with Σm(0) and ΠM(1, 2, 3). Expanded to canonical form that is F = A′ · B′ as a sum of products and F = (A + B′) · (A′ + B) · (A′ + B′) as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
NOR gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
(A + B)′ = A′ · B′
An AND body with bubbles on the inputs only — the “negative-AND” symbol.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 3 gates: 1 AND and 2 NOT. The output F is driven by an AND gate. The longest signal path passes through 2 gates.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a NOR gate from NAND gates only
n1 = NAND(A, A)= A ↑ An2 = NAND(B, B)= B ↑ Bn3 = NAND(n1, n2)= A ↑ A ↑ (B ↑ B)n4 = NAND(n3, n3)= A ↑ A ↑ (B ↑ B) ↑ (A ↑ A ↑ (B ↑ B))
4 NANDs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Building a NOR gate from NOR gates only
n1 = NOR(A, B)= A ↓ B
1 NOR1 level1 gate, 1 level. Verified equivalent to the gate over all 4 input combinations.
Where the NOR gate is used
Like NAND, NOR costs four transistors in static CMOS and is functionally complete on its own. Its most famous application is the Apollo Guidance Computer, built almost entirely from one part type — a Fairchild resistor-transistor-logic Micrologic package containing two 3-input NOR gates — roughly 2,800 such packages, about 5,600 NOR gates, in each Block II machine. Choosing a single gate type simplified qualification and sourcing for a flight computer, which is a concrete reason universality matters outside an exam. Cross-coupling two NOR gates gives the active-high SR latch. Standard parts: 74HC02 and 74HC27.
Gates people confuse with the NOR gate
NOR and OR
same body, one bubble. NOR is OR’s exact complement on all four rows. They differ on rows m0, m1, m2, m3 of the two-input table.
NOR and NAND
the other universal gate. They agree on m₀ and m₃ and differ on m₁ and m₂. The mnemonic that separates them: NAND is 0 only when all inputs are 1; NOR is 1 only when all inputs are 0. They differ on rows m1, m2 of the two-input table.
NOR and XNOR
NOR is 1,0,0,0 and XNOR is 1,0,0,1, so they differ on exactly one row, m₃ (11). They differ on row m3 of the two-input table.
Common mistakes
- ✗ (A + B)′ = A′ + B′✓ De Morgan: (A + B)′ = A′ · B′.
- ✗ Reading NOR as “not all inputs are 1”.✓ That is NAND. NOR is NOT-OR: 1 only for the all-zeros row.
- ✗ Reading the bubble as part of the curved nose.✓ The bubble is a separate circle beyond the nose.
Start from a worked example
Worked examples
- A = 0, B = 0introthe only true row
- Full 2-input truth tableintro1 of 4 rows true
- 3-input NOR, A = 0, B = 0, C = 1coreany high input forces the output low
- NOR is not associative: (A ↓ B) ↓ C vs A ↓ (B ↓ C)coredifferent functions, same symbols
- Functional completeness: NOT, OR, AND from NORcorethe second universal gate
- SR latch from two cross-coupled NORsexamthe active-high memory element
- Bitwise NOR: 0011 0110 ↓ 0100 0001examOR then complement
- NOR as an inverted-input ANDedge casethe alternative symbol
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)
- C. S. Peirce, “A Boolian Algebra with One Constant” (c. 1880), in Collected Papers of Charles Sanders Peirce, vol. 4, Harvard University Press, 1933 — the first statement that one connective suffices.