SR latch from two cross-coupled NORs — NOR gate
exam standardthe active-high memory element
Answer
Q⁺ = 1
Why this example is worth doing
The active-high SR latch, and the counterpart to the NAND latch: inputs idle at 0 and are asserted high. Setting both at once drives both outputs low, breaking the invariant that Q and Q̄ are complements, and on release the winner depends on gate delays. The page insists this is a race with a physical outcome, not an undefined value — the circuit does something, it is just not something you can rely on.
Try your own input in the NOR gate. Truth table, symbol and algebraic form for (A + B)′, the other universal gate.
How the answer is reached
The probed row
S = 0, R = 0, Q = 1
Output table
| S | R | Q | Q⁺ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |