Boolean algebra, truth tables, Karnaugh maps and logic gates

Type or paste anything — an expression, a truth table, a minterm list, a binary number, a line of text. This page works out what it is and shows you every other form of it.

AND is · * & or juxtaposition (AB); OR is + or |; NOT is ¬ ~ ! or a trailing ′; ^ is XOR, never a power; | is OR, never NAND. Paste a truth table, a Σm list, a number in any base, or plain text.

Read as ((A · B) + (¬A · C) + (B · C))

Every form of what you entered

Example

Boolean expression

The function written in algebra, reduced as far as it goes.

Minimal SOP
A′ · C + A · B
Minimal POS
(A + C) · (A′ + B)
POS cost
2 terms / 4 literals

A′ · C + A · B

Minimal SOP: 2 terms / 4 literals — verified exact (Quine–McCluskey, unique minimum).

Truth table

One row per input combination; the output column is the function.

Truth table for F. The leftmost input column is the most significant bit.
ABCF
0000
0011
0100
0111
1000
1010
1101
1111

8 rows · 4 ones · 0 don't-cares

Karnaugh map

The same table laid out so that adjacent cells differ in one variable.

Karnaugh map of the current inputA 2 by 4 Karnaugh map, rows A and columns BC, both axes in Gray-code order so that neighbouring cells differ in one variable. 4 of the 8 cells are 1. 2 groups are outlined, each with a numbered badge and its own dash pattern: 1 covering A′ · C; 2 covering A · B.A\BC0001111001001131204050716112
1. A′ · C · 2. A · B

2 groups · 2×4 map

Gate diagram

The minimal expression built out of physical gates.

Gate diagram of A′ · C + A · B, distinctive shape, ANSI/IEEE Std 91-1984 Logic gate schematic. 3 inputs: A, C and B. 4 gates: 2 AND, 1 OR and 1 NOT. The output F is driven by an OR gate. The longest signal path passes through 3 gates. 1 junction dot marks where a signal fans out to more than one gate. A C B F
Gate diagram of A′ · C + A · B, rectangular shape, IEC 60617-12 Logic gate schematic. 3 inputs: A, C and B. 4 gates: 2 AND, 1 OR and 1 NOT. The output F is driven by an OR gate. The longest signal path passes through 3 gates. 1 junction dot marks where a signal fans out to more than one gate. A C B 1 & & ≥1 F

4 gates · 7 gate inputs

Canonical forms

Every minterm and every maxterm written out in full.

Canonical SOP
A′ · B′ · C + A′ · B · C + A · B · C′ + A · B · C
Canonical POS
(A + B + C) · (A + B′ + C) · (A′ + B + C) · (A′ + B + C′)

Σm(1, 3, 6, 7) · ΠM(0, 2, 4, 5)

Boolean & Minimisation

Turn one expression into every other form of itself, and reduce it with named laws.

Show all 7 boolean & minimisation tools

Gates & Circuits

What each gate does, in both symbol standards, and how to build circuits out of them.

  • Logic gate diagram builder

    Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.

  • Logic circuit → expression

    Wire up gates and read the Boolean expression and truth table back out.

  • Logic gate symbols

    Every gate in both symbol standards, side by side, on a printable one-page chart.

  • AND gate

    Truth table, symbol and algebraic form for A·B, with a live two-input toggle.

  • OR gate

    Truth table, symbol and algebraic form for A + B, with a live two-input toggle.

Show all 15 gates & circuits tools
  • NOT gate

    Truth table, symbol and algebraic form for the inverter, Ā.

  • NAND gate

    Truth table, symbol and algebraic form for (A·B)′, the universal gate.

  • NOR gate

    Truth table, symbol and algebraic form for (A + B)′, the other universal gate.

  • XOR gate

    Truth table, symbol and algebraic form for A ⊕ B, the difference detector.

  • XNOR gate

    Truth table, symbol and algebraic form for A ⊙ B, the equality detector.

  • Buffer

    Truth table, symbol and algebraic form for the non-inverting buffer, and what it is for.

  • Universal gates

    Rebuild any of the other gates using only NAND, or only NOR, with the gate count.

  • Half adder & full adder

    Truth tables, K-maps and circuits for both adders, and the ripple-carry chain.

  • Flip-flops & latches

    SR, D, JK and T: characteristic tables, excitation tables and timing diagrams.

  • Multiplexers & decoders

    Multiplexers from 2:1 to 16:1 and decoders from 2:4 to 4:16, with the selection logic derived.

Numbers & Codes

Convert between bases and representations, and check the codes that detect and fix errors.

Show all 10 numbers & codes tools
  • BCD converter

    Pack and unpack binary-coded decimal, and add with the +6 correction shown.

  • Hamming code

    Encode, inject an error, and watch the syndrome point straight at the flipped bit.

  • Parity & checksum

    Even and odd parity, one’s-complement sums and the Internet checksum, step by step.

  • Huffman coding

    Build the tree from text or from frequencies, with the merge order and canonical codes.

  • Shannon entropy

    Bits per symbol for any distribution, with the surprisal of each symbol shown.

What this is

Every tool here shows its working. When you simplify an expression you get the minimal form and the named law applied at each step — Absorption, Consensus, De Morgan — because you are usually being graded on the method, not the result. When you group a Karnaugh map, the grouping is drawn, and your own grouping is marked correct, redundant or invalid. When you convert a number, the positional arithmetic is written out.

Where a canonical algorithm exists we name it and use it: Quine–McCluskey with Petrick’s method for exact minimisation, so an answer is never a guess that ran out of rewrite rules. Where a function has more than one equally minimal form, you get all of them, rather than one silently chosen and presented as if it were the only one. Nothing is behind an account, a paywall, or a “click to calculate” button, and every page keeps working with no network after your first visit.

Where this comes from

In 1937 a twenty-one-year-old master’s student at MIT noticed that the algebra George Boole had built to describe the laws of thought was the same algebra that describes a network of relay switches — a claim Claude Shannon published the following year as A Symbolic Analysis of Relay and Switching Circuits (Transactions of the AIEE 57(12), 713–723, 1938). That single observation is why a truth table, a Karnaugh map and a circuit diagram are three views of one object, and it is the reason every tool on this site can hand its input to every other.

The full lineage, with sources →