Digital Logic Toolkit — NAND gate
NAND gate: truth table, symbol and Boolean expression
Truth table, symbol and algebraic form for (A·B)′, the universal gate.
The NAND gate
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 1 gate: 1 NAND. The output F is driven by a NAND gate. The longest signal path passes through 1 gate.
Output F0
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = (A · B)′
F = (1 · 1)′ = 0
NAND outputs 0 only when every input is 1.
This is row 4 of 4 — minterm m₃ (A B = 11).
Truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 1 | |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 |
Canonical forms
- Minterms
- Σm(0, 1, 2)
- Maxterms
- ΠM(3)
- Canonical sum of products
- F = A′ · B′ + A′ · B + A · B′
- Canonical product of sums
- F = A′ + B′
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 2 variables, 3 of its 4 cells filled with 1 — cells m₀, m₁, m₂.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
(A · B)′ = A′ + B′
An OR body with bubbles on the inputs only — the “negative-OR” symbol.
| A | B | (A · B)′ | A′ + B′ |
|---|---|---|---|
| 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
The two columns agree on all 4 rows.
NAND from NAND gates only
n1 = NAND(A, B)= A ↑ B
1 NAND1 level1 gate, 1 level. Verified equivalent to the gate over all 4 input combinations.
NAND from NOR gates only
n1 = NOR(A, A)= A ↓ An2 = NOR(B, B)= B ↓ Bn3 = NOR(n1, n2)= A ↓ A ↓ (B ↓ B)n4 = NOR(n3, n3)= A ↓ A ↓ (B ↓ B) ↓ (A ↓ A ↓ (B ↓ B))
4 NORs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Cost
4 transistorsTwo PMOS in parallel and two NMOS in series — the same count as NOR and cheaper than the 6-transistor AND.
- 74HC00 — quad 2-input NAND
- 74HC10 — triple 3-input NAND
- 74HC20 — dual 4-input NAND
- 74HC30 — single 8-input NAND
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the NAND gate does
A NAND gate outputs 0 only when every one of its inputs is 1; on every other row it outputs 1.
Algebraically it is F = (A · B)′, which expands to F = A′ + B′ = A ↑ B. For n inputs, F = (A₁ · A₂ · … · Aₙ)′
- Not associative. (A ↑ B) ↑ C ≠ A ↑ (B ↑ C). For A = 1, B = 1, C = 0: (1↑1)↑0 = 0↑0 = 1 while 1↑(1↑0) = 1↑1 = 0. A “3-input NAND” therefore means (A · B · C)′, never a cascade of 2-input NANDs.
- Functionally complete. Every Boolean function can be built from NAND alone.
- Inverter. NAND(A, A) = A′, by the idempotent law.
NAND gate truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 2 | 1 | 0 | 1 |
| 3 | 1 | 1 | 0 |
| k | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 1 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 0 |
| k | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 1 |
| 2 | 0 | 0 | 1 | 0 | 1 |
| 3 | 0 | 0 | 1 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 | 1 |
| 5 | 0 | 1 | 0 | 1 | 1 |
| 6 | 0 | 1 | 1 | 0 | 1 |
| 7 | 0 | 1 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 | 1 |
| 9 | 1 | 0 | 0 | 1 | 1 |
| 10 | 1 | 0 | 1 | 0 | 1 |
| 11 | 1 | 0 | 1 | 1 | 1 |
| 12 | 1 | 1 | 0 | 0 | 1 |
| 13 | 1 | 1 | 0 | 1 | 1 |
| 14 | 1 | 1 | 1 | 0 | 1 |
| 15 | 1 | 1 | 1 | 1 | 0 |
Boolean expression and canonical forms
At 2 inputs the function is F = (A · B)′, with Σm(0, 1, 2) and ΠM(3). Expanded to canonical form that is F = A′ · B′ + A′ · B + A · B′ as a sum of products and F = A′ + B′ as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
NAND gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
(A · B)′ = A′ + B′
An OR body with bubbles on the inputs only — the “negative-OR” symbol.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 3 gates: 1 OR and 2 NOT. The output F is driven by an OR gate. The longest signal path passes through 2 gates.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a NAND gate from NAND gates only
n1 = NAND(A, B)= A ↑ B
1 NAND1 level1 gate, 1 level. Verified equivalent to the gate over all 4 input combinations.
Building a NAND gate from NOR gates only
n1 = NOR(A, A)= A ↓ An2 = NOR(B, B)= B ↓ Bn3 = NOR(n1, n2)= A ↓ A ↓ (B ↓ B)n4 = NOR(n3, n3)= A ↓ A ↓ (B ↓ B) ↓ (A ↓ A ↓ (B ↓ B))
4 NORs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Where the NAND gate is used
NAND is the workhorse of digital electronics. In static CMOS it costs four transistors — two PMOS in parallel, two NMOS in series — the same as NOR and cheaper than the six-transistor AND. It is functionally complete: everything on this site can be built from NAND gates alone. The 7400 quad 2-input NAND was the first part in the 7400 TTL family and the family is named after it. NAND flash memory is named for the NAND-like series arrangement of its cells. Cross-coupling two NAND gates gives the active-low SR latch that is the basis of every static memory element.
Gates people confuse with the NAND gate
NAND and AND
same body, one bubble. NAND is AND’s exact complement, so they differ on all four rows. They differ on rows m0, m1, m2, m3 of the two-input table.
NAND and NOR
the other universal gate. NAND is 1,1,1,0 and NOR is 1,0,0,0: they agree on m₀ (both 1) and m₃ (both 0) and differ on m₁ and m₂. They differ on rows m1, m2 of the two-input table.
NAND and XOR
NAND is 1,1,1,0 and XOR is 0,1,1,0, so they differ on exactly one row, m₀. Both are 1 when exactly one input is high, which is why they get swapped. They differ on row m0 of the two-input table.
Common mistakes
- ✗ (A · B)′ = A′ · B′✓ De Morgan: (A · B)′ = A′ + B′. The two differ on m₁ and m₂.
- ✗ Chaining 2-input NANDs to get a 3-input NAND.✓ NAND is not associative. Use a real 3-input NAND, or NOT(AND(A, B, C)).
- ✗ Thinking the bubble is on the input.✓ On a NAND the bubble is on the output. Input bubbles with an OR body is the equivalent symbol for the same function.
Start from a worked example
Worked examples
- A = 1, B = 1introthe only false row
- Full 2-input truth tableintro3 of 4 rows true
- 3-input NAND, A = 1, B = 1, C = 0coreone low input forces the output high
- NAND is not associative: (A ↑ B) ↑ C vs A ↑ (B ↑ C)coredifferent functions, same symbols
- Functional completeness: NOT, AND, OR from NANDcorewhy one gate type suffices
- SR latch from two cross-coupled NANDsexamthe memory element
- Bitwise NAND: 1011 0110 ↑ 0110 1101examno processor has this instruction
- NAND as an inverted-input ORedge casethe alternative symbol, and why it is used
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)
- H. M. Sheffer, “A Set of Five Independent Postulates for Boolean Algebras, with Application to Logical Constants,” Transactions of the American Mathematical Society, vol. 14, no. 4, pp. 481–488, October 1913.