Digital Logic Toolkit

Digital Logic Toolkit — Logic gate symbols

Source
https://digitallogictoolkit.com/logic-gate-symbols/
Printed

Logic gate symbols: IEEE and IEC side by side

Every gate in both symbol standards, side by side, on a printable one-page chart.

The chart

NOT and the buffer take exactly one input, so their rows stay at one however this is set.

Both standards are shown here regardless of your setting. Your setting is marked “Your set”, and it controls the running prose below the chart and anything you copy or print from it.

Every logic gate in both symbol standards, with its algebraic form, its truth table and its minterm list. The order pairs each gate with its inverted partner and moves from the one-input gates outwards.
GateDistinctive shape — ANSI/IEEE Std 91-1984 Your setRectangular shape — IEC 60617-12 (constructed metrics) Your setAlgebraic formTruth tableMinterms
buffer
buffer gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 1 input: A. 1 gate: 1 buffer. The output F is driven by a buffer gate. The longest signal path passes through 1 gate. A F
buffer gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 1 input: A. 1 gate: 1 buffer. The output F is driven by a buffer gate. The longest signal path passes through 1 gate. A 1 F

Qualifying symbol 1

F = A
Truth table for the buffer gate: F = A
AF
00
11
Σm(1)
NOT
NOT gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 1 input: A. 1 gate: 1 NOT. The output F is driven by a NOT gate. The longest signal path passes through 1 gate. A F
NOT gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 1 input: A. 1 gate: 1 NOT. The output F is driven by a NOT gate. The longest signal path passes through 1 gate. A 1 F

Qualifying symbol 1

F = A′
Truth table for the NOT gate: F = A′
AF
01
10
Σm(0)
AND
AND gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 AND. The output F is driven by an AND gate. The longest signal path passes through 1 gate. A B F
AND gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 AND. The output F is driven by an AND gate. The longest signal path passes through 1 gate. A B & F

Qualifying symbol &

F = A · B
Truth table for the AND gate: F = A · B
ABF
000
010
100
111
Σm(3)
NAND
NAND gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 NAND. The output F is driven by a NAND gate. The longest signal path passes through 1 gate. A B F
NAND gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 NAND. The output F is driven by a NAND gate. The longest signal path passes through 1 gate. A B & F

Qualifying symbol &

F = (A · B)′
Truth table for the NAND gate: F = (A · B)′
ABF
001
011
101
110
Σm(0, 1, 2)
OR
OR gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 OR. The output F is driven by an OR gate. The longest signal path passes through 1 gate. A B F
OR gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 OR. The output F is driven by an OR gate. The longest signal path passes through 1 gate. A B ≥1 F

Qualifying symbol ≥1

F = A + B
Truth table for the OR gate: F = A + B
ABF
000
011
101
111
Σm(1, 2, 3)
NOR
NOR gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 NOR. The output F is driven by a NOR gate. The longest signal path passes through 1 gate. A B F
NOR gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 NOR. The output F is driven by a NOR gate. The longest signal path passes through 1 gate. A B ≥1 F

Qualifying symbol ≥1

F = (A + B)′
Truth table for the NOR gate: F = (A + B)′
ABF
001
010
100
110
Σm(0)
XOR
XOR gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 XOR. The output F is driven by an XOR gate. The longest signal path passes through 1 gate. A B F
XOR gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 XOR. The output F is driven by an XOR gate. The longest signal path passes through 1 gate. A B =1 F

Qualifying symbol =1

F = A ⊕ B
Truth table for the XOR gate: F = A ⊕ B
ABF
000
011
101
110
Σm(1, 2)
XNOR
XNOR gate, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 XNOR. The output F is driven by an XNOR gate. The longest signal path passes through 1 gate. A B F
XNOR gate, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 XNOR. The output F is driven by an XNOR gate. The longest signal path passes through 1 gate. A B = F

Qualifying symbol =1

F = A ⊙ B
Truth table for the XNOR gate: F = A ⊙ B
ABF
001
010
100
111
Σm(0, 3)

IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.

Notation used on this page
Positive logic
1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
Operators
· AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
Precedence, highest first
( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
Truth-table row order
Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
Minterms and maxterms
Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
Symbol standards
IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
Symbol-set toggle
Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.

Reading a logic gate symbol

In the distinctive-shape set the body shape tells you the function: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and a second concave arc behind an OR body is exclusive-OR.

The bubble is not decoration — it is a NOT. A bubble on the output inverts the function. A bubble on an input inverts that input before the function is applied. Two bubbles on the same wire cancel. Where the bubble sits is the whole difference between AND and NAND, and between a buffer and an inverter.

Input order does not matter for AND, OR, XOR, NAND, NOR and XNOR — all six are commutative — which is why the distinctive-shape set does not label their pins. IEC labels pins on every element, because the rectangle carries no positional meaning of its own.

The two standards, and why you must know which one your course uses

ANSI/IEEE Std 91-1984 distinctive shapes

Dominant in teaching in the United States and the United Kingdom. Each function has its own outline, so a circuit can be read at a glance from the shapes alone. The supplement IEEE Std 91a-1991 adds the dependency notation used for multiplexers and decoders.

IEC 60617-12 rectangular shapes

Dominant in continental Europe and much of Asia. Every element is the same rectangle and the function is carried by a qualifying symbol inside it, which scales to functions that have no traditional shape at all — counters, registers, arithmetic blocks.

The qualifying symbols

&
AND — every input is 1
≥1
OR — at least one input is 1
=1
exclusive-OR — exactly one input is 1
2k+1
odd parity — an odd number of inputs is 1
2k
even parity — an even number of inputs is 1
1
buffer or inverter — the identity function
≥m
majority — at least m inputs are 1

The =1 trap

For two inputs, “exactly one input is 1” and “an odd number of inputs is 1” are the same function, so =1 and XOR coincide. For three or more they differ. =1 is true only when exactly one input is 1, so it gives 0 for 111. The cascade of XOR gates that most textbooks call a “3-input XOR” is true when an odd number of inputs is 1, which includes 111. The correct qualifying symbol for that function is 2k+1, not =1.

Concretely, for A = B = C = 1 a 2k+1 element outputs 1 and a =1 element outputs 0. The two functions differ on exactly one of the eight rows, m₇.

De Morgan equivalent symbols

Each gate’s equivalent symbol: the same function drawn with the bubbles moved.
GateEquivalent symbolIdentity
bufferA triangle with a bubble on both the input and the output. The two bubbles cancel, which is the cleanest demonstration of the bubble-cancellation rule.A = (A′)′
NOTThe inverter is its own equivalent: the bubble may be drawn at either end. Put it at the end where the active-low signal is, so a bubbled output meeting a bubbled input reads as “cancelled”.A′ = A′
ANDAn OR body with bubbles on both inputs and on the output.A · B = (A′ + B′)′
NANDAn OR body with bubbles on the inputs only — the “negative-OR” symbol.(A · B)′ = A′ + B′
ORAn AND body with bubbles on both inputs and on the output.A + B = (A′ · B′)′
NORAn AND body with bubbles on the inputs only — the “negative-AND” symbol.(A + B)′ = A′ · B′
XORAn XOR body with bubbles on both inputs — they cancel. A bubble on one input, or on the output, turns it into an XNOR.A ⊕ B = A′ ⊕ B′
XNORAn XNOR body with bubbles on both inputs. A bubble on one input turns it into an XOR.A ⊙ B = A′ ⊙ B′ = A′ ⊕ B = A ⊕ B′

Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent — which is the whole point of active-low signalling and the reason the equivalent symbol is worth drawing.

Wire conventions

A dot at a crossing means the wires are connected; no dot means they cross without connecting. That is the IEEE Std 315-1975 notation. The standard was formally withdrawn in 2019 with no replacement and is still universally taught and used.

Four-way dotted junctions are avoided because a printing or scanning artefact can turn one into the other; three wires meeting are drawn as two staggered T-junctions instead, which is what this site’s renderer emits.

Printing this chart

The print stylesheet keeps the heading, the notation note, the chart and the truth tables, and drops the interactive chrome, the converter bar and the example links. Both symbol columns print, because the point of the chart is the comparison.

Start from a worked example

Worked examples

Sources

  1. ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
  2. IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)
  3. IEC TS 63064:2018, Preparation of documents used in electrotechnology — Design guidance — the module grid, and the 1:10 line-width-to-module ratio.
  4. Texas Instruments, Overview of IEEE Standard 91-1984: Explanation of Logic Symbols, SDYZ001A.
  5. IEEE Std 315-1975, Graphic Symbols for Electrical and Electronics Diagrams (withdrawn 2019) — the junction-dot convention.
  6. C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.