Digital Logic Toolkit — OR gate
OR gate: truth table, symbol and Boolean expression
Truth table, symbol and algebraic form for A + B, with a live two-input toggle.
The OR gate
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 1 gate: 1 OR. The output F is driven by an OR gate. The longest signal path passes through 1 gate.
Output F1
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = A + B
F = 1 + 1 = 1
OR outputs 1 when at least one input is 1.
This is row 4 of 4 — minterm m₃ (A B = 11).
Truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 1 |
Canonical forms
- Minterms
- Σm(1, 2, 3)
- Maxterms
- ΠM(0)
- Canonical sum of products
- F = A′ · B + A · B′ + A · B
- Canonical product of sums
- F = A + B
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 2 variables, 3 of its 4 cells filled with 1 — cells m₁, m₂, m₃.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
A + B = (A′ · B′)′
An AND body with bubbles on both inputs and on the output.
| A | B | A + B | (A′ · B′)′ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 |
The two columns agree on all 4 rows.
OR from NAND gates only
n1 = NAND(A, A)= A ↑ An2 = NAND(B, B)= B ↑ Bn3 = NAND(n1, n2)= A ↑ A ↑ (B ↑ B)
3 NANDs2 levels3 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.
OR from NOR gates only
n1 = NOR(A, B)= A ↓ Bn2 = NOR(n1, n1)= A ↓ B ↓ (A ↓ B)
2 NORs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.
Cost
6 transistorsA 4-transistor NOR followed by a 2-transistor inverter.
- 74HC32 — quad 2-input OR
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the OR gate does
An OR gate outputs 1 when at least one of its inputs is 1, and 0 only when every input is 0.
Algebraically it is F = A + B. For n inputs, F = A₁ + A₂ + … + Aₙ
- Identity. A + 0 = A
- Null. A + 1 = 1
- Idempotent. A + A = A
- Complement. A + A′ = 1
OR gate truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 2 | 1 | 0 | 1 |
| 3 | 1 | 1 | 1 |
| k | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 1 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 1 |
| k | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 |
| 2 | 0 | 0 | 1 | 0 | 1 |
| 3 | 0 | 0 | 1 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 | 1 |
| 5 | 0 | 1 | 0 | 1 | 1 |
| 6 | 0 | 1 | 1 | 0 | 1 |
| 7 | 0 | 1 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 | 1 |
| 9 | 1 | 0 | 0 | 1 | 1 |
| 10 | 1 | 0 | 1 | 0 | 1 |
| 11 | 1 | 0 | 1 | 1 | 1 |
| 12 | 1 | 1 | 0 | 0 | 1 |
| 13 | 1 | 1 | 0 | 1 | 1 |
| 14 | 1 | 1 | 1 | 0 | 1 |
| 15 | 1 | 1 | 1 | 1 | 1 |
Boolean expression and canonical forms
At 2 inputs the function is F = A + B, with Σm(1, 2, 3) and ΠM(0). Expanded to canonical form that is F = A′ · B + A · B′ + A · B as a sum of products and F = A + B as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
OR gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
A + B = (A′ · B′)′
An AND body with bubbles on both inputs and on the output.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 4 gates: 1 AND and 3 NOT. The output F is driven by a NOT gate. The longest signal path passes through 3 gates.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a OR gate from NAND gates only
n1 = NAND(A, A)= A ↑ An2 = NAND(B, B)= B ↑ Bn3 = NAND(n1, n2)= A ↑ A ↑ (B ↑ B)
3 NANDs2 levels3 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.
Building a OR gate from NOR gates only
n1 = NOR(A, B)= A ↓ Bn2 = NOR(n1, n1)= A ↓ B ↓ (A ↓ B)
2 NORs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.
Where the OR gate is used
OR is any-of logic: an alarm that fires if the door sensor or the window sensor or the motion sensor trips is a 3-input OR. Bitwise, OR sets bits — x | 0x80 forces bit 7 high and leaves the rest alone, because x + 0 = x. In switch terms, OR is two switches in parallel. Static CMOS OR is six transistors, a four-transistor NOR plus an inverter. Note that natural-language “or” is usually exclusive (“tea or coffee”) while the gate called OR is inclusive; that mismatch is the root of the OR/XOR confusion. Standard part: 74HC32, quad 2-input OR.
Gates people confuse with the OR gate
OR and XOR
the single most common confusion in Boolean algebra. OR and XOR agree on m₀, m₁ and m₂ and differ only on m₃ (11): OR gives 1 (“at least one”), XOR gives 0 (“exactly one, not both”). They differ on row m3 of the two-input table.
OR and NOR
same body, one bubble. NOR is OR’s exact complement on all four rows. They differ on rows m0, m1, m2, m3 of the two-input table.
OR and AND
the +/· notation swap. They differ on m₁ and m₂. They differ on rows m1, m2 of the two-input table.
Common mistakes
- ✗ Reading 1 + 1 = 10, as in binary addition.✓ In Boolean algebra 1 + 1 = 1; + is OR, not addition. Addition with a carry is the half adder.
- ✗ Assuming “A or B” excludes “both”.✓ The OR gate is inclusive. The exclusive version is XOR.
- ✗ Drawing the input leads stopping at a straight vertical back edge.✓ The IEEE OR back edge is a concave arc, and the leads terminate on the arc.
Start from a worked example
Worked examples
- A = 1, B = 0introinclusive, not exclusive
- Full 2-input truth tableintro3 of 4 rows true
- 3-input OR, A = 0, B = 0, C = 1coreone high input dominates
- 8-input OR as a zero detectorcorecomplement of the wide AND
- Bitwise OR: 1011 0110 | 0000 1111coresetting the low nibble
- OR from NOR gates onlyexamuniversal-gate construction
- OR as an inverted-input NANDexamthe alternative IEEE symbol
- Wired-OR on an open-drain busedge caseOR without a gate
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)