Flip-flops and latches: SR, D, JK and T

A latch is level-sensitive. While its enable is asserted it is transparent: the output follows the input continuously, glitches and all, and it stops following only when the enable is removed. A flip-flop is edge-triggered. It looks at its inputs at one instant — here, the rising edge of the clock — and ignores them the rest of the time.

Run the same input through both and the difference is visible rather than verbal. Select the D latch above and set EN high for several consecutive columns: Q copies D in every one of them. Select the D flip-flop and Q changes once per column, at the edge, and holds in between. That single clock of delay is the reason a flip-flop is drawn as z⁻¹ in signal-processing diagrams, and the reason a register built from latches on one clock phase is not a register at all.

The vocabulary is not universal: some texts call an edge-triggered device a “clocked latch”, and older parts labelled “latch” are pulse-triggered. On this page latch means level-sensitive and flip-flop means edge-triggered, without exception.

Add an enable: S_int = EN·S and R_int = EN·R. Now the latch only listens while EN is asserted. The forbidden state has not gone anywhere — it is simply unreachable while EN is low.

Remove it properly by tying the two inputs together through an inverter: S = EN·D and R = EN·D′. S and R can now never both be 1, because D and D′ can never both be 1. That is precisely why the D latch exists, and its characteristic equation Q⁺ = EN·D + EN′·Q carries no constraint at all — the one device on this page whose equation is unconditional apart from the two flip-flops with a single input.

The dynamic-input indicator — a wedge drawn inside the symbol on the clock pin — is what marks an edge-triggered input. A wedge alone means the active edge is the rising one; a wedge with a bubble outside the symbol means the falling one. Every flip-flop on this page is positive-edge-triggered.

Master–slave is not the same thing. A master–slave pair is two latches on opposite clock phases: the master is transparent while the clock is high and the slave copies it when the clock falls. The output changes on one edge, which looks like edge triggering from outside, but the master was listening for a whole half cycle. A true edge-triggered flip-flop — the six-NAND structure, or a master–slave built from edge-triggered stages — samples in a narrow window around the edge only.

Setup and hold. The inputs must be stable for t_su before the active edge and t_h after it. A transition inside that window is a violation, not a coin toss: the part’s datasheet makes no guarantee at all, and the output may go metastable. Outputs change t_co after the edge, never on it, which is what makes it possible to chain flip-flops back to back without the second one seeing the first one’s new value on the same edge.

Asynchronous inputs. Where a part has them, PRE_n (preset) and CLR_n (clear) are active-LOW and override the clock entirely — the flip-flop sets or clears the moment they are asserted, whatever the clock is doing. Asserting both at once is illegal for the same reason S = R = 1 is.

Q⁺ = D, and nothing else. Its excitation table above reads D = Q⁺ in every row with no don’t-cares, which is exactly why sequential design with D flip-flops is the easy case: whatever next-state expression the state table gives you is the D input expression, with no further work.

Internally it is either a master–slave pair of D latches on opposite clock phases, or the classic six-NAND edge-triggered structure. Both appear on real parts and both behave identically at the pins for the purpose of this page.

The JK is the SR flip-flop with the forbidden state given a job. Tie S = J·Q′ and R = K·Q: S and R can never both be 1, because Q and Q′ cannot both be 1. The combination that used to be illegal, J = K = 1, now means toggle, and the characteristic equation Q⁺ = J·Q′ + K′·Q covers all four rows with no constraint attached.

Q⁺ = T ⊕ Q: hold when T is 0, toggle when T is 1. Its excitation table reads T = Q ⊕ Q⁺ — apply a 1 exactly when the state has to change — which makes it the natural element for counters, where every bit’s job is to change on a schedule.

There is no standard 74-series T flip-flop. You make one from a JK by tying J = K = T, or from a D flip-flop with D = T ⊕ Q, which costs one XOR gate.

They are the same information read in opposite directions, and using the wrong one is the commonest way to get stuck on a sequential-design question.

A characteristic table answers analysis: given the inputs and the present state, what does the state become? It is a truth table for Q⁺. An excitation table answers synthesis: I need this transition — what must I apply to get it? It is that same relation inverted, which is why don’t-cares appear in it and never in the characteristic table. Every excitation entry marked X above was produced by finding more than one legal input vector that causes the transition and observing that they disagree about that input, not by copying a book.

A T flip-flop with T tied to 1 — or a JK with both inputs tied high — toggles on every active edge, so its output is the clock divided by two. Chain n of them, each clocked by the previous stage’s output, and you have an n-bit ripple (asynchronous) counter running through all 2ⁿ states: Q₀ at f/2, Q₁ at f/4, Q₂ at f/8.

Clocking each stage from the previous stage’s Q with positive-edge parts makes the count run down; clocking from Q_n, or using negative-edge parts, makes it run up. Either way the stages do not change together: stage k changes k propagation delays after the clock edge, so the outputs pass through wrong intermediate values on every carry — 011 → 010 → 000 → 100 on the 3 → 4 transition of a three-bit counter. Decode those outputs combinationally and you decode the glitches too. Synchronous counters, where every flip-flop takes the same clock and the inputs carry the enable logic, exist to remove exactly that.

74HC74 — dual D, positive-edge, with active-low preset and clear. 74HC76 and 74LS73 — dual JK. 74HC75 — quad transparent D latch. 74HC373 — octal transparent latch. 74HC374 — octal positive-edge D flip-flop.