T flip-flop as a divide-by-two — flip-flops
exam standardtoggle, and what it is for
Answer
Q⁺ column 0110
Why this example is worth doing
A T flip-flop with T held high toggles every clock, so its output is a square wave at half the clock frequency. Chain n of them and you have a binary counter and a divide-by-2ⁿ. The page shows the timing diagram with the ripple delay visible between stages, which is where asynchronous counters get their reputation — each stage's transition is late by one propagation delay, and the errors accumulate.
Try your own input in the Flip-flops & latches. SR, D, JK and T: characteristic tables, excitation tables and timing diagrams.
How the answer is reached
Output table
| T | Q | Q⁺ |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |