Digital Logic Toolkit

Digital Logic Toolkit — AND gate

Source
https://digitallogictoolkit.com/and-gate/
Printed

AND gate: truth table, symbol and Boolean expression

Truth table, symbol and algebraic form for A·B, with a live two-input toggle.

The AND gate

AND gate with 2 inputs, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 1 gate: 1 AND. The output F is driven by an AND gate. The longest signal path passes through 1 gate. A B F
AND gate with 2 inputs, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 1 gate: 1 AND. The output F is driven by an AND gate. The longest signal path passes through 1 gate. A B & F
Distinctive shape — ANSI/IEEE Std 91-1984Rectangular shape — IEC 60617-12 (constructed metrics) — F = A · B at 2 inputs

IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.

Circuit description

Logic gate schematic. 2 inputs: A and B. 1 gate: 1 AND. The output F is driven by an AND gate. The longest signal path passes through 1 gate.

Inputs
1
1

Output F1

Notation used on this page
Positive logic
1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
Operators
· AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
Precedence, highest first
( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
Truth-table row order
Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
Minterms and maxterms
Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
Symbol standards
IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
Symbol-set toggle
Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.

Evaluation

F = A · B

F = 1 · 1 = 1

AND outputs 1 only when every input is 1.

This is row 4 of 4 — minterm m₃ (A B = 11).

Truth table

Truth table for F = A · B. Select a row to set the inputs to it.
kABF
000
010
100
111

Canonical forms

Minterms
Σm(3)
Maxterms
ΠM(0, 1, 2)
Canonical sum of products
F = A · B
Canonical product of sums
F = (A + B) · (A + B′) · (A′ + B)

mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.

Karnaugh map

The map for this function is 2 variables, 1 of its 4 cells filled with 1 — cells m₃.

Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.

De Morgan equivalent

A · B = (A′ + B′)′

An OR body with bubbles on both inputs and on the output.

Both sides of A · B = (A′ + B′)′, column by column.
ABA · B(A′ + B′)′
0000
0100
1000
1111

The two columns agree on all 4 rows.

AND from NAND gates only

  1. n1 = NAND(A, B)= A ↑ B
  2. n2 = NAND(n1, n1)= A ↑ B ↑ (A ↑ B)

2 NANDs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.

Note:The second NAND has both inputs tied together, which makes it an inverter, so it undoes the first NAND’s inversion.

AND from NOR gates only

  1. n1 = NOR(A, A)= A ↓ A
  2. n2 = NOR(B, B)= B ↓ B
  3. n3 = NOR(n1, n2)= A ↓ A ↓ (B ↓ B)

3 NORs2 levels3 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.

Cost

6 transistorsA 4-transistor NAND followed by a 2-transistor inverter. That is why NAND, not AND, is the natural primitive in silicon.

  • 74HC08 — quad 2-input AND
  • 74HC11 — triple 3-input AND
  • 74HC21 — dual 4-input AND
Building each two-input gate from one primitive. Every count is measured from the netlist that draws it and verified by exhaustive simulation.
TargetNAND gatesNAND levelsNOR gatesNOR levels
buffer2222
NOT1111
AND2232
NAND1143
OR3222
NOR4311
XOR4353
XNOR5443

What the AND gate does

An AND gate outputs 1 when every one of its inputs is 1, and 0 otherwise.

Algebraically it is F = A · B. For n inputs, F = A₁ · A₂ · … · Aₙ

  • Identity. A · 1 = A — holding one input at 1 passes the other through.
  • Null. A · 0 = 0 — holding one input at 0 forces the output to 0.
  • Idempotent. A · A = A
  • Complement. A · A′ = 0

AND gate truth table

AND gate with 2 inputs: F = A · B. Σm(3) · ΠM(0, 1, 2)
kABF
0000
1010
2100
3111
AND gate with 3 inputs: F = A · B · C. Σm(7) · ΠM(0, 1, 2, 3, 4, 5, 6)
kABCF
00000
10010
20100
30110
41000
51010
61100
71111
AND gate with 4 inputs: F = A · B · C · D. Σm(15) · ΠM(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
kABCDF
000000
100010
200100
300110
401000
501010
601100
701110
810000
910010
1010100
1110110
1211000
1311010
1411100
1511111

Boolean expression and canonical forms

At 2 inputs the function is F = A · B, with Σm(3) and ΠM(0, 1, 2). Expanded to canonical form that is F = A · B as a sum of products and F = (A + B) · (A + B′) · (A′ + B) as a product of sums.

Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.

AND gate symbol

Distinctive shape — ANSI/IEEE Std 91-1984

The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.

The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.

Rectangular shape — IEC 60617-12 (constructed metrics)

The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.

De Morgan equivalent symbol

A · B = (A′ + B′)′

An OR body with bubbles on both inputs and on the output.

De Morgan equivalent of the AND gate, A · B, drawn with IEEE 91-1984 distinctive shapes Logic gate schematic. 2 inputs: A and B. 4 gates: 1 OR and 3 NOT. The output F is driven by a NOT gate. The longest signal path passes through 3 gates. A B F
De Morgan equivalent of the AND gate, A · B, drawn with IEC 60617-12 rectangular symbols Logic gate schematic. 2 inputs: A and B. 4 gates: 1 OR and 3 NOT. The output F is driven by a NOT gate. The longest signal path passes through 3 gates. A B 1 1 ≥1 1 F
Distinctive shape — ANSI/IEEE Std 91-1984Rectangular shape — IEC 60617-12 (constructed metrics) — the equivalent circuit, with the bubbles drawn as inverters

IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.

Circuit description

Logic gate schematic. 2 inputs: A and B. 4 gates: 1 OR and 3 NOT. The output F is driven by a NOT gate. The longest signal path passes through 3 gates.

Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.

Building a AND gate from NAND gates only

  1. n1 = NAND(A, B)= A ↑ B
  2. n2 = NAND(n1, n1)= A ↑ B ↑ (A ↑ B)

2 NANDs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.

Note:The second NAND has both inputs tied together, which makes it an inverter, so it undoes the first NAND’s inversion.

Building a AND gate from NOR gates only

  1. n1 = NOR(A, A)= A ↓ A
  2. n2 = NOR(B, B)= B ↓ B
  3. n3 = NOR(n1, n2)= A ↓ A ↓ (B ↓ B)

3 NORs2 levels3 gates, 2 levels. Verified equivalent to the gate over all 4 input combinations.

Where the AND gate is used

An AND gate is an enable: hold one input at 1 and the gate passes the other input unchanged (A · 1 = A); hold it at 0 and the output is forced to 0 (A · 0 = 0). That is exactly how clock gating and bitwise masking work — x & 0x0F keeps the low nibble and clears the rest. In switch terms, AND is two switches in series. In static CMOS an AND gate is six transistors: a four-transistor NAND followed by a two-transistor inverter, which is why NAND rather than AND is the natural primitive in silicon.

Gates people confuse with the AND gate

AND and OR

the + in A + B is OR, not arithmetic addition. AND and OR differ on rows m₁ (01) and m₂ (10), where AND gives 0 and OR gives 1. They differ on rows m1, m2 of the two-input table.

OR gate

AND and NAND

identical body, one bubble. NAND is AND’s exact complement, so the two differ on every one of the four rows. They differ on rows m0, m1, m2, m3 of the two-input table.

NAND gate

AND and XNOR

both output 1 on m₃ (11). They differ on exactly one row, m₀ (00), where AND gives 0 and XNOR gives 1. They differ on row m0 of the two-input table.

XNOR gate

Common mistakes

  • ✗ Writing A + B for “A AND B”.✓ AND is A · B or AB; + is OR.
  • ✗ Reading the semicircular nose as a bubble.✓ The nose is the body. A bubble is a small circle outside the body, on the output lead.
  • ✗ Assuming a 3-input AND is 1 on three of its eight rows.✓ It is 1 on exactly one row, m₇.

Start from a worked example

Worked examples

Sources

  1. G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
  2. C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
  3. A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
  4. ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
  5. IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)