8-input AND as an address decoder line — AND gate

corewide fan-in, 1/256 selectivity

Answer

output 1 on 1 of 256 input patterns

Why this example is worth doing

An eight-input AND is true on one of two hundred and fifty-six patterns, which is precisely what an address decoder needs: one output line asserted for one address. The page uses it to introduce fan-in cost, because an eight-input CMOS AND is not one stage — it is a tree, and the delay grows with the logarithm of the input count. That is the reason wide decoders are built from layers of small gates rather than from single wide ones.

Try your own input in the AND gate. Truth table, symbol and algebraic form for A·B, with a live two-input toggle.

How the answer is reached

Truth table

Truth table — columns #, A, B, C, D, E, F, G, H, A · B · C · D · E · F · G · H
#ABCDEFGHA · B · C · D · E · F · G · H
0000000000
1000000010
2000000100
3000000110
4000001000
5000001010
6000001100
7000001110
8000010000
9000010010
10000010100
11000010110
12000011000
13000011010
14000011100
15000011110
16000100000
17000100010
18000100100
19000100110
20000101000
21000101010
22000101100
23000101110
24000110000
25000110010
26000110100
27000110110
28000111000
29000111010
30000111100
31000111110
Warning:

First 32 of 256 rows.

Compare with

Open the AND gate

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements