Wire up gates and read the Boolean expression and truth table back out.
Describe the circuit
Netlist
One gate per line: signal = GATE(input, …). "# in:" names the primary inputs and "# out:" the primary outputs; internal wires are declared by their first assignment and line order does not matter.
Gate connection table
Connection table: one row per gate. Every input is chosen from the declared signals, so a gate cannot reference a node that does not exist.
Output
Type
Inputs
Actions
s1
Sum
c1
c2
Cout
Signals
Signals: every named node in the circuit, its kind, how many gate inputs it drives, and whether it is a primary output.
Signal
Kind
Output
Actions
primary inputfans out to 2 pins
primary inputfans out to 2 pins
primary inputfans out to 2 pins
internal wirefans out to 2 pins
primary output
internal wire
internal wire
primary output
Note:Two different circuits can compute the same function. This tells you what your circuit computes; it does not claim your circuit is the only one, or the cheapest.
Output Sum
As wiredA ⊕ B ⊕ Cin
Read as((A ⊕ B) ⊕ Cin)
Negations pushed inA ⊕ B ⊕ Cinalready pushed in
2 gates · 2 levels on the longest path to this output.
How the expression was read off, gate by gate
Forward labelling for Sum: each gate's output, in the order you would work them out by hand
Step
Gate
Inputs
Output signal
Expression it now carries
1
XOR
A, B
s1
A ⊕ B
2
XOR
s1, Cin
Sum
A ⊕ B ⊕ Cin
Note:This is one correct circuit for the expression, not the only one. The notes below name every choice the drawing made that a different tool would make differently.
Distinctive shape — ANSI/IEEE Std 91-1984Rectangular shape — IEC 60617-12 (constructed metrics)IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
···
Gate list for Sum: every gate, its inputs and the expression it carries
Gate
Type
Inputs
Output expression
XOR
A, B
A ⊕ B
XOR
s1, Cin
A ⊕ B ⊕ Cin
AND
A, B
A · B
AND
s1, Cin
(A ⊕ B) · Cin
OR
c1, c2
A · B + (A ⊕ B) · Cin
Circuit description and netlist
Logic gate schematic. 3 inputs: A, B and Cin. 5 gates: 2 AND, 1 OR and 2 XOR. The output Sum is driven by an XOR gate. The longest signal path passes through 3 gates. 4 junction dots mark where a signal fans out to more than one gate.
The circuit computes Sum = A ⊕ B ⊕ Cin, read as ((A ⊕ B) ⊕ Cin).
Netlist for Sum: every gate, its inputs and the expression it carries
Gate
Type
Inputs
Output expression
s1
XOR
A, B
A ⊕ B
Sum
XOR
s1, Cin
A ⊕ B ⊕ Cin
c1
AND
A, B
A · B
c2
AND
s1, Cin
(A ⊕ B) · Cin
Cout
OR
c1, c2
A · B + (A ⊕ B) · Cin
Truth table, with a column for every gate
Truth table for Sum, with a column for every gate output
Row
A
B
Cin
s1
Sum
Sum
0
0
0
0
0
0
0
1
0
0
1
0
1
1
2
0
1
0
1
1
1
3
0
1
1
1
0
0
4
1
0
0
1
1
1
5
1
0
1
1
0
0
6
1
1
0
0
0
0
7
1
1
1
0
1
1
Σm(1, 2, 4, 7)ΠM(0, 3, 5, 6)
Output Cout
As wiredA · B + (A ⊕ B) · Cin
Read as((A · B) + ((A ⊕ B) · Cin))
Negations pushed inA · B + (A ⊕ B) · Cinalready pushed in
4 gates · 3 levels on the longest path to this output.
How the expression was read off, gate by gate
Forward labelling for Cout: each gate's output, in the order you would work them out by hand
Step
Gate
Inputs
Output signal
Expression it now carries
1
AND
A, B
c1
A · B
2
XOR
A, B
s1
A ⊕ B
3
AND
s1, Cin
c2
(A ⊕ B) · Cin
4
OR
c1, c2
Cout
A · B + (A ⊕ B) · Cin
Note:This is one correct circuit for the expression, not the only one. The notes below name every choice the drawing made that a different tool would make differently.
Distinctive shape — ANSI/IEEE Std 91-1984Rectangular shape — IEC 60617-12 (constructed metrics)IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
···
Gate list for Cout: every gate, its inputs and the expression it carries
Gate
Type
Inputs
Output expression
XOR
A, B
A ⊕ B
XOR
s1, Cin
A ⊕ B ⊕ Cin
AND
A, B
A · B
AND
s1, Cin
(A ⊕ B) · Cin
OR
c1, c2
A · B + (A ⊕ B) · Cin
Circuit description and netlist
Logic gate schematic. 3 inputs: A, B and Cin. 5 gates: 2 AND, 1 OR and 2 XOR. The output Cout is driven by an OR gate. The longest signal path passes through 3 gates. 4 junction dots mark where a signal fans out to more than one gate.
The circuit computes Cout = A · B + (A ⊕ B) · Cin, read as ((A · B) + ((A ⊕ B) · Cin)).
Netlist for Cout: every gate, its inputs and the expression it carries
Gate
Type
Inputs
Output expression
s1
XOR
A, B
A ⊕ B
Sum
XOR
s1, Cin
A ⊕ B ⊕ Cin
c1
AND
A, B
A · B
c2
AND
s1, Cin
(A ⊕ B) · Cin
Cout
OR
c1, c2
A · B + (A ⊕ B) · Cin
Truth table, with a column for every gate
Truth table for Cout, with a column for every gate output
Row
A
B
Cin
c1
s1
c2
Cout
Cout
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
2
0
1
0
0
1
0
0
0
3
0
1
1
0
1
1
1
1
4
1
0
0
0
1
0
0
0
5
1
0
1
0
1
1
1
1
6
1
1
0
1
0
0
1
1
7
1
1
1
1
0
0
1
1
Σm(3, 5, 6, 7)ΠM(0, 1, 2, 4)
Reading a circuit back into algebra
Work from the primary inputs forwards. Label each gate’s output with the expression its inputs carry, substitute those labels into the next gate along, and the primary output’s label is the circuit’s expression. That is exactly what the forward-walk table beside the editor does, one gate per row, so the answer is a derivation rather than a claim.
The truth table is then generated from that expression, which is why the two can never disagree: they are the same function evaluated twice.
Why a netlist and not a drag-and-drop canvas
A textual netlist is typeable, pasteable, shareable in a URL, diffable and usable on a phone. A canvas adds a coordinate system that has nothing to do with the logic, cannot be prerendered, and makes half-drawn, invalid circuits representable. The canonical teaching model for this direction — Logisim’s Combinational Analysis — is several synchronised views over one structure, and that is the model here with the canvas removed.
Combinational, sequential and feedback loops
A circuit whose output feeds back into its own input is not combinational and has no Boolean expression: cross-coupled NOR gates are a latch, and its output depends on its history rather than only on its inputs. The tool names the loop it found rather than printing a wrong expression, and points at the flip-flops page, which is where that circuit is analysed properly with a characteristic table.
One function, many circuits
Two different circuits can compute the same function. Reading a circuit tells you what it computes; it does not tell you that your circuit is the only one or the cheapest one. To find out, hand the expression to the simplifier and compare gate counts.
G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)