AND-OR-INVERT: (A·B + C)′ as one complex gate — circuit to expression
exam standardreads back as (A·B + C)′
Answer
A′ · C′ + B′ · C′ (output column 10101000)
Why this example is worth doing
An AOI21 cell — AND-OR-Invert with a two-input AND and one straight input — drawn as one symbol because that is how it exists in a standard cell library. In CMOS it is a single stage of six transistors, cheaper and faster than the AND, OR and inverter it replaces. The page uses it to explain why synthesised netlists look nothing like the textbook AND-OR drawings, and why an inverting output is the default rather than an inconvenience.
Try your own input in the Logic circuit → expression. Wire up gates and read the Boolean expression and truth table back out.
How the answer is reached
Gate list
| Node | Gate | Inputs |
|---|---|---|
| a1 | and | A, B |
| o1 | or | a1, C |
| inv | not | o1 |
Quine–McCluskey
| # | Term |
|---|---|
| 1 | A′ · C′ |
| 2 | B′ · C′ |
| # | Cover |
|---|---|
| 1 | A′ · C′ + B′ · C′ |
Warning:
2 term(s), 4 literal(s); 2 essential prime implicant(s).
Truth table
| # | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 0 |