Two AND gates and an OR forming a 2:1 selector — circuit to expression
introreads back as S̄·A + S·B
Answer
B · S + A · S′ (output column 00011011)
Why this example is worth doing
The gate-level 2:1 multiplexer: two AND gates gated by S and its complement, feeding an OR. Reading it back gives the standard selector expression, and the page names it, because recognising a mux in a schematic is what lets a student replace nine gates with one part. It also makes the point that the inverter on S is not optional — without it both AND gates can be enabled at once and the OR sees a meaningless union rather than a selection.
Try your own input in the Logic circuit → expression. Wire up gates and read the Boolean expression and truth table back out.
How the answer is reached
Gate list
| Node | Gate | Inputs |
|---|---|---|
| n1 | not | S |
| g1 | and | A, n1 |
| g2 | and | B, S |
| g3 | or | g1, g2 |
Quine–McCluskey
| # | Term |
|---|---|
| 1 | B · S |
| 2 | A · S′ |
| 3 | A · B |
| # | Cover |
|---|---|
| 1 | B · S + A · S′ |
Warning:
2 term(s), 4 literal(s); 2 essential prime implicant(s).
Truth table
| # | A | B | S | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 1 |