Full adder carry-out from two half adders — circuit to expression
edge casereads back as A·B + C·(A ⊕ B)
Answer
B · C + A · C + A · B (output column 00010111)
Why this example is worth doing
The carry-out of a full adder as it is actually built — from two half adders and an OR — rather than as its minimal SOP. The two forms are equal, and the tool proves it by comparing truth tables, but they are different hardware: the built version shares the XOR that the sum output already needs, so it is cheaper in context even though it has more literals on paper. The page uses this to separate expression cost from circuit cost.
Try your own input in the Logic circuit → expression. Wire up gates and read the Boolean expression and truth table back out.
How the answer is reached
Gate list
| Node | Gate | Inputs |
|---|---|---|
| x1 | xor | A, B |
| a1 | and | A, B |
| a2 | and | x1, C |
| o1 | or | a1, a2 |
Quine–McCluskey
| # | Term |
|---|---|
| 1 | B · C |
| 2 | A · C |
| 3 | A · B |
| # | Cover |
|---|---|
| 1 | B · C + A · C + A · B |
Warning:
3 term(s), 6 literal(s); 3 essential prime implicant(s).
Truth table
| # | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 0 |
| 5 | 1 | 0 | 1 | 1 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 1 |