3-bit ripple counter from T flip-flops
edge casethe first sequential system
Answer
Q2⁺ column 00011110, Q1⁺ column 01100110, Q0⁺ column 10101010
Why this example is worth doing
Three toggle flip-flops in a chain count from zero to seven and wrap. The page uses it to close the sequential section with a complete system rather than a component, and to expose the ripple problem honestly: because each stage clocks the next, the outputs are briefly inconsistent after every transition, and decoding them combinationally produces glitches. That is the argument for synchronous counters, which is where the next course starts.
Try your own input in the Flip-flops & latches. SR, D, JK and T: characteristic tables, excitation tables and timing diagrams.
How the answer is reached
Output table
| Q2 | Q1 | Q0 | Q2⁺ | Q1⁺ | Q0⁺ |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 |