Digital Logic Toolkit

Digital Logic Toolkit — Multiplexers & decoders

Source
https://digitallogictoolkit.com/multiplexers-decoders/
Printed

4:16 decoder from two 3:8 decoders — multiplexers and decoders

edge casewhy decoders have enable pins

Answer

EN lower column 10, EN upper column 01

Why this example is worth doing

Cascading two smaller decoders into a larger one works only because each has an enable input: the high-order address bit enables one half and disables the other. This is the reason an enable pin is on the part at all, and it is the same technique used to build large memories from small ones. The page generalises the construction and gives the part count, closing the section on a systems-level note.

Try your own input in the Multiplexers & decoders. Multiplexers from 2:1 to 16:1 and decoders from 2:4 to 4:16, with the selection logic derived.

How the answer is reached

Output table

Output table — columns A3, EN lower, EN upper
A3EN lowerEN upper
010
101

Compare with

Open the Multiplexers & decoders

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements