Digital Logic Toolkit

Digital Logic Toolkit — Multiplexers & decoders

Source
https://digitallogictoolkit.com/multiplexers-decoders/
Printed

2:1 mux, S = 0 — multiplexers and decoders

introthe selector equation

Answer

Y = 1

Why this example is worth doing

With the select line low the mux passes its first input. The expression S̄·I₀ + S·I₁ is worth reading as a pattern rather than a formula: each data input is ANDed with the select condition that chooses it, and the results are ORed. Every larger mux and every decoder on this page is that pattern repeated, which is why the page starts with the smallest possible case.

Try your own input in the Multiplexers & decoders. Multiplexers from 2:1 to 16:1 and decoders from 2:4 to 4:16, with the selection logic derived.

How the answer is reached

The probed row

S = 0, I0 = 1, I1 = 0

Output table

Output table — columns S, I0, I1, Y
SI0I1Y
0000
0010
0101
0111
1000
1011
1100
1111

Compare with

Open the Multiplexers & decoders

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements