8:1 mux implementing F(A,B,C) = Σm(1,2,4,7) — multiplexers and decoders
corea mux as a lookup table
Answer
8 rows, 4 true (1, 2, 4, 7)
Why this example is worth doing
Feed the variables into the select lines and wire each data input to the corresponding row of the truth table, and the multiplexer computes any three-variable function with no logic design at all. This is a lookup table, and it is precisely how an FPGA implements combinational logic. The page makes that connection explicitly, because it reframes the multiplexer from a routing part into the fundamental programmable element.
Try your own input in the Multiplexers & decoders. Multiplexers from 2:1 to 16:1 and decoders from 2:4 to 4:16, with the selection logic derived.
How the answer is reached
Truth table
| # | A | B | C | A ⊕ B ⊕ C |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 1 |