1:4 demultiplexer routing one input to four — multiplexers and decoders

exam standardthe mux run backwards

Answer

Y0 = 0, Y1 = 0, Y2 = 1, Y3 = 0

Why this example is worth doing

A demultiplexer is a decoder whose outputs are gated by a data line, and it is the inverse of the multiplexer: one input, many outputs, select chooses which one gets the data. The page pairs it with the mux to make the symmetry explicit, and notes that mux-and-demux pairs are how a single wire is shared between many sources and destinations — the whole basis of time-division multiplexing.

Try your own input in the Multiplexers & decoders. Multiplexers from 2:1 to 16:1 and decoders from 2:4 to 4:16, with the selection logic derived.

How the answer is reached

The probed row

S1 = 1, S0 = 0, D = 1

Output table

Output table — columns S1, S0, D, Y0, Y1, Y2, Y3
S1S0DY0Y1Y2Y3
0000000
0011000
0100000
0110100
1000000
1010010
1100000
1110001

Compare with

Open the Multiplexers & decoders

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements