((A·B)′·C)′ — logic gate diagram
core2 NAND gates (4 AND/NOT primitive nodes); bubble cancellation
Answer
4 gates, 3 inputs; output column 10101011
Why this example is worth doing
Two NAND gates in series, which is not the same as an AND followed by a NAND — the bubble on the first output meets the bubble implied at the second input and the two cancel. The page uses this diagram to teach bubble pushing as a visual form of involution and De Morgan: an inversion at an output and an inversion at the input it drives annihilate, so you can slide bubbles along wires freely to make a network's logic readable. It is the single most useful schematic-reading skill in the course.
Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.
How the answer is reached
Netlist
| Node | Gate | Inputs |
|---|---|---|
| g0 | and | i0, i1 |
| g1 | not | g0 |
| g2 | and | g1, i2 |
| g3 | not | g2 |
Truth table
| # | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 1 |