A·B + B·C + A·C — logic gate diagram
exam standard5 primitive gates (4 with a 3-input OR); the majority voter
Answer
4 gates, 3 inputs; output column 00010111
Why this example is worth doing
The three-input majority function, output 1 when at least two inputs are. It is drawn as three ANDs feeding one OR, and it is the carry-out of a full adder, the core of a triple-redundant voter, and one of the few functions where the minimal SOP really is symmetric in all three variables. The page points at all three uses, because recognising a standard function in a schematic is worth more than being able to trace it gate by gate.
Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.
How the answer is reached
Netlist
| Node | Gate | Inputs |
|---|---|---|
| g0 | and | i0, i1 |
| g1 | and | i1, i2 |
| g2 | and | i0, i2 |
| g3 | or | g0, g1, g2 |
Truth table
| # | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 0 |
| 5 | 1 | 0 | 1 | 1 |
| 6 | 1 | 1 | 0 | 1 |
| 7 | 1 | 1 | 1 | 1 |