(A + B)·(C + D) — logic gate diagram
intro3 primitive gates, 2 levels, 4 inputs
Answer
3 gates, 4 inputs; output column 0000011101110111
Why this example is worth doing
A two-level OR-AND network — the product-of-sums shape — which is what you draw when the minimal form is a POS rather than an SOP. Structurally it is the mirror image of the previous example, and putting them next to each other is the fastest way to see that AND-OR and OR-AND are the same amount of hardware. The page notes that CMOS actually implements the inverting versions more cheaply, which is why real synthesis output is full of NAND and NOR rather than the shapes drawn in textbooks.
Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.
How the answer is reached
Netlist
| Node | Gate | Inputs |
|---|---|---|
| g0 | or | i0, i1 |
| g1 | or | i2, i3 |
| g2 | and | g0, g1 |
Truth table
| # | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 2 | 0 | 0 | 1 | 0 | 0 |
| 3 | 0 | 0 | 1 | 1 | 0 |
| 4 | 0 | 1 | 0 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 | 1 |
| 6 | 0 | 1 | 1 | 0 | 1 |
| 7 | 0 | 1 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 | 1 |
| 10 | 1 | 0 | 1 | 0 | 1 |
| 11 | 1 | 0 | 1 | 1 | 1 |
| 12 | 1 | 1 | 0 | 0 | 0 |
| 13 | 1 | 1 | 0 | 1 | 1 |
| 14 | 1 | 1 | 1 | 0 | 1 |
| 15 | 1 | 1 | 1 | 1 | 1 |