Ā·B + A·B̄ — logic gate diagram

core5 gates as SOP vs 1 XOR gate

Answer

5 gates, 2 inputs; output column 0110

Why this example is worth doing

XOR built the long way, out of two inverters, two ANDs and an OR. Drawing it explicitly is worth doing once, because the single XOR symbol otherwise looks like it comes from nowhere. The page renders both and puts the gate counts side by side: five gates and three levels against one gate and one level. It also shows the fan-out dots where A and B each drive two loads, which is the first diagram on the site where a signal branches and the junction notation has to be explained.

Try your own input in the Logic gate diagram builder. Draw an expression as a gate schematic in IEEE or IEC symbols and copy it as an image.

How the answer is reached

Netlist

Netlist — columns Node, Gate, Inputs
NodeGateInputs
g0noti0
g1andg0, i1
g2noti1
g3andi0, g2
g4org1, g3

Truth table

Truth table — columns #, A, B, F
#ABF
0000
1011
2101
3110

Compare with

Open this example in the Logic gate diagram builder

The field arrives filled in with this example’s input.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements