Digital Logic Toolkit — NOT gate
NOT gate (inverter): truth table, symbol and Boolean expression
Truth table, symbol and algebraic form for the inverter, Ā.
The NOT gate
The NOT gate takes exactly one input, so there is no input-count control.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 1 input: A. 1 gate: 1 NOT. The output F is driven by a NOT gate. The longest signal path passes through 1 gate.
Output F0
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = A′
F = 1′ = 0
NOT outputs the opposite of its input.
This is row 2 of 2 — minterm m₁ (A = 1).
Truth table
| k | A | F |
|---|---|---|
| 0 | 1 | |
| 1 | 0 |
Canonical forms
- Minterms
- Σm(0)
- Maxterms
- ΠM(1)
- Canonical sum of products
- F = A′
- Canonical product of sums
- F = A′
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 1 variables, 1 of its 2 cells filled with 1 — cells m₀.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
A′ = A′
The inverter is its own equivalent: the bubble may be drawn at either end. Put it at the end where the active-low signal is, so a bubbled output meeting a bubbled input reads as “cancelled”.
NOT from NAND gates only
n1 = NAND(A, A)= A ↑ A
1 NAND1 level1 gate, 1 level. Verified equivalent to the gate over all 2 input combinations.
NOT from NOR gates only
n1 = NOR(A, A)= A ↓ A
1 NOR1 level1 gate, 1 level. Verified equivalent to the gate over all 2 input combinations.
Cost
2 transistorsOne PMOS pull-up and one NMOS pull-down: the smallest logic gate there is, and the model every other static CMOS gate is built on.
- 74HC04 — hex inverter
- 74HC14 — hex Schmitt-trigger inverter, for cleaning up slow edges
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the NOT gate does
A NOT gate — an inverter — outputs 1 when its input is 0 and 0 when its input is 1.
Algebraically it is F = A′. For n inputs, F = A′ — the inverter takes exactly one input.
- Involution. (A′)′ = A — two inverters in series are a buffer.
- Complement. A · A′ = 0 and A + A′ = 1
- Other spellings. Ā, ¬A, ~A, !A and A′ all mean the same thing.
NOT gate truth table
| k | A | F |
|---|---|---|
| 0 | 0 | 1 |
| 1 | 1 | 0 |
Boolean expression and canonical forms
At 1 inputs the function is F = A′, with Σm(0) and ΠM(1). Expanded to canonical form that is F = A′ as a sum of products and F = A′ as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
NOT gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
A′ = A′
The inverter is its own equivalent: the bubble may be drawn at either end. Put it at the end where the active-low signal is, so a bubbled output meeting a bubbled input reads as “cancelled”.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a NOT gate from NAND gates only
n1 = NAND(A, A)= A ↑ A
1 NAND1 level1 gate, 1 level. Verified equivalent to the gate over all 2 input combinations.
Building a NOT gate from NOR gates only
n1 = NOR(A, A)= A ↓ A
1 NOR1 level1 gate, 1 level. Verified equivalent to the gate over all 2 input combinations.
Where the NOT gate is used
The CMOS inverter is the smallest logic gate there is: two transistors, one PMOS pull-up and one NMOS pull-down. Every other static CMOS gate is built on the same pull-up/pull-down-network idea. Inverters are also how active-low signalling is expressed — a reset line drawn with an overbar asserts when it is LOW, and the bubble on the symbol tells you so. A chain of inverters is used as a delay line, and an even number of them as a buffer. Standard parts: 74HC04 (hex inverter) and 74HC14 (hex Schmitt-trigger inverter).
Gates people confuse with the NOT gate
NOT and buffer
the same triangle without the bubble. The buffer outputs A and the inverter outputs A′, so they differ on both rows. They differ on rows m0, m1 of the two-input table.
NOT and NAND
a NAND with its inputs tied together is an inverter, which is why a 7400 can stand in for a hex inverter in a pinch. The two are related by construction rather than by a differing row.
NOT and NOR
likewise, NOR(A, A) = A′, and a 3-input NOR with two inputs grounded is an inverter. The two are related by construction rather than by a differing row.
Common mistakes
- ✗ (A · B)′ = A′ · B′✓ De Morgan gives (A · B)′ = A′ + B′. The two differ on m₁ and m₂.
- ✗ Dropping the bubble and drawing a bare triangle.✓ A bare triangle is a buffer. The bubble is the whole function.
- ✗ Writing A′′ and treating it as something new.✓ (A′)′ = A — involution.
Start from a worked example
Worked examples
- A = 1introthe whole gate in one row
- Full truth tableintro2 rows, output is the complement
- Double inversion: (A′)′coretwo inverters cancel
- NOT from a NAND with tied inputscoreone gate, both inputs shorted
- NOT from a NOR with tied inputscorethe dual construction
- Bitwise NOT of 1011 0110examone's complement of a byte
- Inverter on an active-low enableexambubbles as polarity, not logic
- Ring oscillator: three inverters in a loopedge casewhen a combinational circuit has no answer
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)