Digital Logic Toolkit

Digital Logic Toolkit — NOT gate

Source
https://digitallogictoolkit.com/not-gate/
Printed

NOT from a NAND with tied inputs — NOT gate

coreone gate, both inputs shorted

Answer

1 NAND gate realising A′

Why this example is worth doing

Tie both inputs of a NAND together and it inverts, because A·A = A by idempotence and the output bubble does the rest. This is step one of every NAND-only conversion and the reason NAND is universal at all. The page shows the idempotent law doing the work explicitly, since students often assume tying inputs is a special electrical rule rather than an algebraic consequence.

Try your own input in the NOT gate. Truth table, symbol and algebraic form for the inverter, Ā.

How the answer is reached

Gate list

Gate list — columns Node, Gate, Inputs
NodeGateInputs
g1nandA, A

NAND-only realisation

A ↑ AA′— 1 NAND gates, verified by reading the network back out.

Truth table

Truth table — columns #, A, A ↑ A
#AA ↑ A
001
110

Compare with

Open the NOT gate

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements