NOT from a NOR with tied inputs — NOT gate
corethe dual construction
Answer
1 NOR gate realising A′
Why this example is worth doing
The NOR version of the same trick, resting on A + A = A instead. Having both on the page matters because the two universal families are not interchangeable in practice: a NAND-only design and a NOR-only design of the same function generally have different gate counts, and which is cheaper depends on the function. The universal gates page tabulates that comparison; this entry is where the question first comes up.
Try your own input in the NOT gate. Truth table, symbol and algebraic form for the inverter, Ā.
How the answer is reached
Gate list
| Node | Gate | Inputs |
|---|---|---|
| g1 | nor | A, A |
NOR-only realisation
A ↓ AA′— 1 NOR gates, verified by reading the network back out.
Truth table
| # | A | A ↓ A |
|---|---|---|
| 0 | 0 | 1 |
| 1 | 1 | 0 |