Digital Logic Toolkit

Digital Logic Toolkit — NOT gate

Source
https://digitallogictoolkit.com/not-gate/
Printed

Inverter on an active-low enable — NOT gate

exam standardbubbles as polarity, not logic

Answer

EN̄ = 1

Why this example is worth doing

Real signals are frequently active low, written with an overbar or a leading slash, and an inverter is how you cross between conventions. The page's point is that a bubble on a schematic can mean either "this gate inverts" or "this signal is active low", and that the two readings look identical on paper. Getting them confused inverts the behaviour of a design, and it is a mistake practising engineers still make.

Try your own input in the NOT gate. Truth table, symbol and algebraic form for the inverter, Ā.

How the answer is reached

The probed row

EN = 0

Output table

Output table — columns EN, EN̄
ENEN̄
01
10

Compare with

Open the NOT gate

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements