Digital Logic Toolkit — XNOR gate
XNOR gate: truth table, symbol and Boolean expression
Truth table, symbol and algebraic form for A ⊙ B, the equality detector.
The XNOR gate
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 1 gate: 1 XNOR. The output F is driven by an XNOR gate. The longest signal path passes through 1 gate.
Output F1
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = A ⊙ B
F = 1 ⊙ 1 = 1
XNOR outputs 1 when its two inputs are equal.
This is row 4 of 4 — minterm m₃ (A B = 11).
Truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 1 | 0 | 0 | |
| 1 | 1 | 1 |
Canonical forms
- Minterms
- Σm(0, 3)
- Maxterms
- ΠM(1, 2)
- Canonical sum of products
- F = A′ · B′ + A · B
- Canonical product of sums
- F = (A + B′) · (A′ + B)
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 2 variables, 2 of its 4 cells filled with 1 — cells m₀, m₃.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
A ⊙ B = A′ ⊙ B′ = A′ ⊕ B = A ⊕ B′
An XNOR body with bubbles on both inputs. A bubble on one input turns it into an XOR.
| A | B | A ⊙ B | A′ ⊙ B′ |
|---|---|---|---|
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 |
The two columns agree on all 4 rows.
XNOR from NAND gates only
n1 = NAND(A, B)= A ↑ Bn2 = NAND(A, n1)= A ↑ (A ↑ B)n3 = NAND(B, n1)= B ↑ (A ↑ B)n4 = NAND(n2, n3)= A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B))n5 = NAND(n4, n4)= A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B)) ↑ (A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B)))
5 NANDs4 levels5 gates, 4 levels. Verified equivalent to the gate over all 4 input combinations.
XNOR from NOR gates only
n1 = NOR(A, B)= A ↓ Bn2 = NOR(A, n1)= A ↓ (A ↓ B)n3 = NOR(B, n1)= B ↓ (A ↓ B)n4 = NOR(n2, n3)= A ↓ (A ↓ B) ↓ (B ↓ (A ↓ B))
4 NORs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Cost
12 transistorsThe same as XOR: twelve transistors static, six with transmission gates.
- 74HC7266 — quad 2-input XNOR with normal outputs
- 74x266 — the older quad XNOR, whose outputs are open-drain and therefore need pull-up resistors — a classic breadboard trap
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the XNOR gate does
An XNOR gate outputs 1 when its two inputs are equal, and 0 when they differ.
Algebraically it is F = A ⊙ B, which expands to F = (A ⊕ B)′ = A · B + A′ · B′ = (A + B′) · (A′ + B). For n inputs, A cascade of n−1 XNOR gates, whose parity sense alternates with width: 3 inputs gives odd parity, 4 gives even parity, 5 gives odd again.
- Commutative. A ⊙ B = B ⊙ A
- Identity. A ⊙ 1 = A
- Inverting. A ⊙ 0 = A′
- Self. A ⊙ A = 1 and A ⊙ A′ = 0
- Also written. A ≡ B, A XNOR B, A ↔ B — the biconditional of propositional logic.
XNOR gate truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 2 | 1 | 0 | 0 |
| 3 | 1 | 1 | 1 |
| k | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 1 |
| k | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 2 | 0 | 0 | 1 | 0 | 0 |
| 3 | 0 | 0 | 1 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 | 1 |
| 6 | 0 | 1 | 1 | 0 | 1 |
| 7 | 0 | 1 | 1 | 1 | 0 |
| 8 | 1 | 0 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 | 1 |
| 10 | 1 | 0 | 1 | 0 | 1 |
| 11 | 1 | 0 | 1 | 1 | 0 |
| 12 | 1 | 1 | 0 | 0 | 1 |
| 13 | 1 | 1 | 0 | 1 | 0 |
| 14 | 1 | 1 | 1 | 0 | 0 |
| 15 | 1 | 1 | 1 | 1 | 1 |
Boolean expression and canonical forms
At 2 inputs the function is F = A ⊙ B, with Σm(0, 3) and ΠM(1, 2). Expanded to canonical form that is F = A′ · B′ + A · B as a sum of products and F = (A + B′) · (A′ + B) as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
XNOR gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
A ⊙ B = A′ ⊙ B′ = A′ ⊕ B = A ⊕ B′
An XNOR body with bubbles on both inputs. A bubble on one input turns it into an XOR.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 3 gates: 2 NOT and 1 XNOR. The output F is driven by an XNOR gate. The longest signal path passes through 2 gates.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a XNOR gate from NAND gates only
n1 = NAND(A, B)= A ↑ Bn2 = NAND(A, n1)= A ↑ (A ↑ B)n3 = NAND(B, n1)= B ↑ (A ↑ B)n4 = NAND(n2, n3)= A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B))n5 = NAND(n4, n4)= A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B)) ↑ (A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B)))
5 NANDs4 levels5 gates, 4 levels. Verified equivalent to the gate over all 4 input combinations.
Building a XNOR gate from NOR gates only
n1 = NOR(A, B)= A ↓ Bn2 = NOR(A, n1)= A ↓ (A ↓ B)n3 = NOR(B, n1)= B ↓ (A ↓ B)n4 = NOR(n2, n3)= A ↓ (A ↓ B) ↓ (B ↓ (A ↓ B))
4 NORs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Where the XNOR gate is used
XNOR is the equality comparator: A ⊙ B is 1 exactly when the two bits match, so an n-bit equality test is n XNOR gates feeding one n-input AND. That is precisely how a magnitude comparator’s “A = B” output and a cache tag comparator are built. It is also the even-parity element, subject to the width caveat above, and it converts Gray code back to binary in the complement direction. In propositional logic it is the biconditional A ↔ B, “A if and only if B”. Silicon cost is the same as XOR. Standard parts: 74HC7266, and the older 74x266 whose open-drain outputs need pull-ups.
Gates people confuse with the XNOR gate
XNOR and XOR
exact complement on every row. XOR means “not equal”, XNOR means “equal”. They differ on rows m0, m1, m2, m3 of the two-input table.
XNOR and AND
XNOR is 1,0,0,1 and AND is 0,0,0,1, so they differ on exactly one row, m₀ (00). Both give 1 for 11, which is why they get swapped. They differ on row m0 of the two-input table.
XNOR and NOR
XNOR is 1,0,0,1 and NOR is 1,0,0,0, so they differ on exactly one row, m₃ (11). They differ on row m3 of the two-input table.
Common mistakes
- ✗ Assuming a chain of XNORs is always even parity.✓ It alternates with width: three inputs give odd parity, four give even, five give odd again.
- ✗ Writing XNOR as (A · B)′ + (A′ · B′)′.✓ It is A · B + A′ · B′ — no complement on the terms.
- ✗ Drawing an XOR body with no bubble and calling it XNOR.✓ XNOR is the XOR body plus an output bubble.
Start from a worked example
Worked examples
- A = 1, B = 1introagreement gives 1
- Full 2-input truth tableintrotrue when the inputs agree
- 3-input XNOR, A = 0, B = 0, C = 1coreparity, not all-equal
- A ⊙ 0 and A ⊙ 1corethe mirror of the XOR identity
- Bitwise XNOR: 1011 0110 ⊙ 0110 1101coreagreement mask between two bytes
- XNOR from five NAND gatesexamone gate more than XOR
- XNOR expanded to SOPexamthe complement pair of XOR's SOP
- Even-parity generator over four bitsedge casethe transmit-side parity circuit
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)