3-input XNOR, A = 0, B = 0, C = 1 — XNOR gate

coreparity, not all-equal

Answer

output 1

Why this example is worth doing

The trap on this page, and a sharper one than the XOR version. Two inputs low and one high are plainly not all equal, yet the chained XNOR outputs 1 — because a chain of XNORs computes parity, with the accumulated inversions deciding which parity, and not agreement. An all-equal detector over three inputs is a different circuit entirely, which the page draws beside this one so the two are never confused again.

Try your own input in the XNOR gate. Truth table, symbol and algebraic form for A ⊙ B, the equality detector.

How the answer is reached

The probed row

A = 0, B = 0, C = 11Row 1 of 8.

Truth table

Truth table — columns #, A, B, C, A ⊙ B ⊙ C
#ABCA ⊙ B ⊙ C
00000
10011
20101
30110
41001
51010
61100
71111

Compare with

Open this example in the XNOR gate

The field arrives filled in with this example’s input.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements