XNOR from five NAND gates — XNOR gate

exam standardone gate more than XOR

Answer

5 NAND gates realising A′ · B′ + A · B

Why this example is worth doing

Building XNOR from NANDs costs one more gate than XOR, since the cheapest route is the four-NAND XOR followed by a NAND inverter. The page uses this to make a point about universal-gate costs generally: they are not symmetric, and the count depends on which primitive you start from, so a design decision to standardise on one gate type has a real and asymmetric price that shows up function by function.

Try your own input in the XNOR gate. Truth table, symbol and algebraic form for A ⊙ B, the equality detector.

How the answer is reached

Gate list

Gate list — columns Node, Gate, Inputs
NodeGateInputs
g1nandA, B
g2nandA, g1
g3nandg1, B
g4nandg2, g3
g5nandg4, g4

NAND-only realisation

A ↑ (A ↑ B) ↑ (A ↑ B ↑ B) ↑ (A ↑ (A ↑ B) ↑ (A ↑ B ↑ B))A′ · B′ + A · B5 NAND gates, verified by reading the network back out.

Truth table

Truth table — columns #, A, B, A ↑ (A ↑ B) ↑ (A ↑ B ↑ B) ↑ (A ↑ (A ↑ B) ↑ (A ↑ B ↑ B))
#ABA ↑ (A ↑ B) ↑ (A ↑ B ↑ B) ↑ (A ↑ (A ↑ B) ↑ (A ↑ B ↑ B))
0001
1010
2100
3111

Compare with

Open the XNOR gate

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements