XOR from NOR gates only — universal gates

edge caseone more than the NAND version

Answer

5 NOR gates realising A′ · B + A · B′

Why this example is worth doing

XOR costs five NOR gates against four NAND gates, an asymmetry with a reason: XOR's cheapest factoring is a sum of products, which suits the NAND family. The page closes the topic here, having shown that "universal" is a statement about possibility and never about cost. Which gate to standardise on depends on the shape of the function you are implementing, and this pair of numbers is the smallest honest demonstration of that.

Try your own input in the Universal gates. Rebuild any of the other gates using only NAND, or only NOR, with the gate count.

How the answer is reached

Gate list

Gate list — columns Node, Gate, Inputs
NodeGateInputs
g1norA, B
g2norA, g1
g3norg1, B
g4norg2, g3
g5norg4, g4

NOR-only realisation

A ↓ (A ↓ B) ↓ (A ↓ B ↓ B) ↓ (A ↓ (A ↓ B) ↓ (A ↓ B ↓ B))A′ · B + A · B′5 NOR gates, verified by reading the network back out.

Truth table

Truth table — columns #, A, B, A ↓ (A ↓ B) ↓ (A ↓ B ↓ B) ↓ (A ↓ (A ↓ B) ↓ (A ↓ B ↓ B))
#ABA ↓ (A ↓ B) ↓ (A ↓ B ↓ B) ↓ (A ↓ (A ↓ B) ↓ (A ↓ B ↓ B))
0000
1011
2101
3110

Compare with

Open this example in the Universal gates

The field arrives filled in with this example’s input.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • Sheffer, “A Set of Five Independent Postulates for Boolean Algebras” (1913)
  • Shannon, “A Symbolic Analysis of Relay and Switching Circuits” (1938)