NOT, OR, AND from NOR — universal gates

exam standardthe dual cost table

Answer

3 NOR gates realising A · B

Why this example is worth doing

The NOR-family costs, transposed from the NAND family: OR is cheap at two gates and AND is dear at three. Setting the two tables side by side is what makes the duality concrete rather than asserted, and it yields the design rule the page exists to deliver — minimise to SOP and implement in NAND, or minimise to POS and implement in NOR, and never mix the decision.

Try your own input in the Universal gates. Rebuild any of the other gates using only NAND, or only NOR, with the gate count.

How the answer is reached

Gate list

Gate list — columns Node, Gate, Inputs
NodeGateInputs
g1norA, A
g2norB, B
g3norg1, g2

NOR-only realisation

A ↓ A ↓ (B ↓ B)A · B3 NOR gates, verified by reading the network back out.

Truth table

Truth table — columns #, A, B, A ↓ A ↓ (B ↓ B)
#ABA ↓ A ↓ (B ↓ B)
0000
1010
2100
3111

Compare with

Open this example in the Universal gates

The field arrives filled in with this example’s input.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • Sheffer, “A Set of Five Independent Postulates for Boolean Algebras” (1913)
  • Shannon, “A Symbolic Analysis of Relay and Switching Circuits” (1938)