Digital Logic Toolkit — Buffer
Buffer gate: truth table, symbol and tri-state buffers
Truth table, symbol and algebraic form for the non-inverting buffer, and what it is for.
The buffer gate
The buffer gate takes exactly one input, so there is no input-count control.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 1 input: A. 1 gate: 1 buffer. The output F is driven by a buffer gate. The longest signal path passes through 1 gate.
Output F1
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = A
F = 1 = 1
A buffer outputs its input unchanged.
This is row 2 of 2 — minterm m₁ (A = 1).
Truth table
| k | A | F |
|---|---|---|
| 0 | 0 | |
| 1 | 1 |
Canonical forms
- Minterms
- Σm(1)
- Maxterms
- ΠM(0)
- Canonical sum of products
- F = A
- Canonical product of sums
- F = A
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 1 variables, 1 of its 2 cells filled with 1 — cells m₁.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
A = (A′)′
A triangle with a bubble on both the input and the output. The two bubbles cancel, which is the cleanest demonstration of the bubble-cancellation rule.
buffer from NAND gates only
n1 = NAND(A, A)= A ↑ An2 = NAND(n1, n1)= A ↑ A ↑ (A ↑ A)
2 NANDs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 2 input combinations.
buffer from NOR gates only
n1 = NOR(A, A)= A ↓ An2 = NOR(n1, n1)= A ↓ A ↓ (A ↓ A)
2 NORs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 2 input combinations.
Cost
4 transistorsTwo inverters back to back.
- 74HC125 — quad tri-state buffer, active-low enable
- 74HC126 — the same but with an active-high enable
- 74HC244 — octal tri-state buffer / line driver
- 7407 — hex open-collector high-voltage buffer
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the buffer gate does
A buffer outputs exactly its input. It changes nothing logically and everything electrically.
Algebraically it is F = A. For n inputs, F = A — the buffer takes exactly one input.
- Identity function. F = A. Any number of buffers in series is still a buffer.
- From inverters. (A′)′ = A — two inverters in series are a buffer.
- One-input gates. A 1-input AND is a buffer (A · 1 = A) and so is a 1-input OR (A + 0 = A).
buffer gate truth table
| k | A | F |
|---|---|---|
| 0 | 0 | 0 |
| 1 | 1 | 1 |
Boolean expression and canonical forms
At 1 inputs the function is F = A, with Σm(1) and ΠM(0). Expanded to canonical form that is F = A as a sum of products and F = A as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
buffer gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
A = (A′)′
A triangle with a bubble on both the input and the output. The two bubbles cancel, which is the cleanest demonstration of the bubble-cancellation rule.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a buffer gate from NAND gates only
n1 = NAND(A, A)= A ↑ An2 = NAND(n1, n1)= A ↑ A ↑ (A ↑ A)
2 NANDs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 2 input combinations.
Building a buffer gate from NOR gates only
n1 = NOR(A, A)= A ↓ An2 = NOR(n1, n1)= A ↓ A ↓ (A ↓ A)
2 NORs2 levels2 gates, 2 levels. Verified equivalent to the gate over all 2 input combinations.
Where the buffer gate is used
Four real reasons a buffer exists. Fan-out: a gate output can only drive so many inputs before its rise time and noise margin collapse, and a buffer restores drive. Tri-state bus sharing: several drivers share one wire, exactly one has its enable asserted at a time and the rest go to high impedance — two drivers enabled at once is bus contention, a direct short from supply to ground through two output stages, which is why bus enables are usually driven from a decoder that guarantees one-hot selection by construction. Delay and pulse shaping: a chain of buffers is a controlled delay, and ANDing a signal with an inverted delayed copy of itself makes a short pulse on each rising edge. Level shifting and isolation: open-collector buffers translate between voltage domains and drive LEDs and relays that a logic output cannot. Cost: four transistors in CMOS. Standard parts: 74HC125, 74HC126, 74HC244 and the open-collector 7407.
Gates people confuse with the buffer gate
buffer and NOT
the same triangle, and the bubble is the only difference. They differ on both rows — the single most consequential missing-bubble error a student can make. They differ on rows m0, m1 of the two-input table.
buffer and AND
a 1-input AND gate is a buffer, A · 1 = A, which is why some netlist formats emit AND(A) where you expected a buffer. The two are related by construction rather than by a differing row.
buffer and OR
likewise a 1-input OR is a buffer, A + 0 = A. The two are related by construction rather than by a differing row.
Common mistakes
- ✗ “A buffer does nothing, so I can delete it.”✓ Logically true, electrically false — and in a tri-state design deleting it removes the ability to disconnect from the bus.
- ✗ Treating Z as a third logic level you can feed into an AND gate.✓ Z is undriven. The receiving input floats and its value is undefined.
- ✗ Enabling two bus drivers at once “because both have valid data”.✓ That is contention. Use a decoder or a multiplexer so exactly one driver is ever on.
Start from a worked example
Worked examples
- A = 1introoutput equals input
- Full truth tableintro2 rows, identity
- Fan-out: one signal driving twelve inputscorewhy the gate exists at all
- Three-state buffer, enable = 1corethe enabled case
- Three-state buffer, enable = 0corethe value that is not a value
- Bus with four three-state driversexamthe rule that makes shared buses work
- Buffer as a delay elementexamtime as the only difference
- Open-collector buffer driving an LEDedge casethe interface use
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)