Buffer as a delay element — buffer gate

exam standardtime as the only difference

Answer

Y = 0

Why this example is worth doing

Chains of buffers are used deliberately to add delay, for clock alignment or to meet a hold-time constraint. It is the clearest example on the site of a circuit whose entire purpose is invisible in its truth table, because a truth table has no time axis. The page uses that gap to motivate timing diagrams, which is the representation the flip-flops page needs and the one combinational tools cannot provide.

Try your own input in the Buffer. Truth table, symbol and algebraic form for the non-inverting buffer, and what it is for.

How the answer is reached

The probed row

A = 0

Output table

Output table — columns A, Y
AY
00
11

Compare with

Open the Buffer

This input is entered in the tool itself — it is too rich for a link to carry.

Note:

Notation this page assumes

  • Symbols: · is AND, + is OR, ⊕ is XOR, a prime or an overline is NOT. The field also takes ∧ ∨ ¬ ~ ! & | and the words.
  • Operator precedence, tightest first: NOT, then AND (including juxtaposition), then XOR/XNOR, then NAND/NOR, then OR, then IMPLIES, then IFF.
  • Gate symbols follow whichever standard the header toggle is set to: ANSI/IEEE Std 91-1984 distinctive shapes, or IEC 60617-12 rectangles.

Sources

  • ANSI/IEEE Std 91-1984, Graphic Symbols for Logic Functions
  • IEC 60617-12, Graphical Symbols for Diagrams — Binary Logic Elements