4-bit ripple-carry: 1011 + 0110 — adders
corecarry out of the top bit
Answer
10001
Why this example is worth doing
Four full adders chained, each waiting for the carry below it. The result needs five bits, so in a fixed four-bit register this is an overflow — and whether that matters depends on whether the operands are signed, which the two's complement page takes up. The page shows the carry propagating stage by stage and gives the delay as four gate-pair delays, which is the motivation for everything that follows it.
Try your own input in the Half adder & full adder. Truth tables, K-maps and circuits for both adders, and the ripple-carry chain.
How the answer is reached
01011 + 00110 (5-bit, unsigned)
| operand | bits | hex | unsigned | signed |
|---|---|---|---|---|
| A | 01011 | 0x0B | 11 | 11 |
| B | 00110 | 0x06 | 6 | 6 |
| row | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|
| carry in | 1 | 1 | 1 | 0 | 0 |
| A | 0 | 1 | 0 | 1 | 1 |
| + B | 0 | 0 | 1 | 1 | 0 |
| result | 1 | 0 | 0 | 0 | 1 |
C = 0 · V = 1 · N = 1 · Z = 0
unsigned11 + 6 = 17, kept as 17— fits in the width
signed11 + 6 = 17, kept as -15— V = 1: the signed answer is wrong
C is carry-out (unsigned overflow); V is carry-into-MSB XOR carry-out-of-MSB (signed overflow). They are independent: either, both or neither can be set.