Digital Logic Toolkit — XOR gate
XOR gate: truth table, symbol and Boolean expression
Truth table, symbol and algebraic form for A ⊕ B, the difference detector.
The XOR gate
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 1 gate: 1 XOR. The output F is driven by an XOR gate. The longest signal path passes through 1 gate.
Output F0
Notation used on this page
- Positive logic
- 1 = HIGH = asserted, 0 = LOW = deasserted. An active-low signal is written with an overbar in figures and a trailing _n in copyable text, for example CLR_n.
- Operators
- · AND (also written by juxtaposition, AB) · + OR · ′ complement (postfix; an overbar in figures) · ⊕ XOR · ⊙ XNOR · ↑ NAND (Sheffer stroke) · ↓ NOR (Peirce arrow).
- Precedence, highest first
- ( ) then ′ then · (including juxtaposition) then ⊕ and ⊙ then ↑ and ↓ then +. The parser echoes the fully parenthesised reading back, and warns without blocking when ⊕, ↑ or ↓ appears un-parenthesised beside · or +, because textbooks disagree there.
- Truth-table row order
- Binary counting order from all-zeros to all-ones. The first-listed variable is the most significant bit. Row index k is the integer value of the input vector, and the row is labelled mₖ.
- Minterms and maxterms
- Σm(…) lists the rows where F = 1. ΠM(…) lists the rows where F = 0. Mᵢ complements a variable wherever bit i is 1 — the opposite way round from mᵢ.
- Symbol standards
- IEEE means ANSI/IEEE Std 91-1984 with its 91a-1991 supplement — the distinctive shapes. IEC means IEC 60617-12 — the rectangular shapes with a qualifying symbol. The header toggle switches every figure on the page between them.
- Symbol-set toggle
- Both symbol standards are in this page’s HTML. The toggle in the header chooses which one is drawn, before the first frame is painted, and it changes nothing else on the page — not a truth table, not a gate count, not an answer.
Evaluation
F = A ⊕ B
F = 1 ⊕ 1 = 0
XOR outputs 1 when an odd number of its inputs is 1 — for two inputs, when exactly one is 1.
This is row 4 of 4 — minterm m₃ (A B = 11).
Truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 |
Canonical forms
- Minterms
- Σm(1, 2)
- Maxterms
- ΠM(0, 3)
- Canonical sum of products
- F = A′ · B + A · B′
- Canonical product of sums
- F = (A + B) · (A′ + B′)
mk is the row where F = 1 and Mk the row where F = 0. Mk complements a variable wherever bit k is 1 — the opposite way round from mk.
Karnaugh map
The map for this function is 2 variables, 2 of its 4 cells filled with 1 — cells m₁, m₂.
Karnaugh map solver — group this function on a Karnaugh map, with this function carried across.
De Morgan equivalent
A ⊕ B = A′ ⊕ B′
An XOR body with bubbles on both inputs — they cancel. A bubble on one input, or on the output, turns it into an XNOR.
| A | B | A ⊕ B | A′ ⊕ B′ |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
The two columns agree on all 4 rows.
XOR from NAND gates only
n1 = NAND(A, B)= A ↑ Bn2 = NAND(A, n1)= A ↑ (A ↑ B)n3 = NAND(B, n1)= B ↑ (A ↑ B)n4 = NAND(n2, n3)= A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B))
4 NANDs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
XOR from NOR gates only
n1 = NOR(A, B)= A ↓ Bn2 = NOR(A, A)= A ↓ An3 = NOR(B, B)= B ↓ Bn4 = NOR(n2, n3)= A ↓ A ↓ (B ↓ B)n5 = NOR(n1, n4)= A ↓ B ↓ (A ↓ A ↓ (B ↓ B))
5 NORs3 levels5 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Cost
12 transistorsTwelve transistors in fully static CMOS, or six in a transmission-gate implementation. XOR is expensive in silicon relative to NAND.
- 74HC86 — quad 2-input XOR
| Target | NAND gates | NAND levels | NOR gates | NOR levels |
|---|---|---|---|---|
| buffer | 2 | 2 | 2 | 2 |
| NOT | 1 | 1 | 1 | 1 |
| AND | 2 | 2 | 3 | 2 |
| NAND | 1 | 1 | 4 | 3 |
| OR | 3 | 2 | 2 | 2 |
| NOR | 4 | 3 | 1 | 1 |
| XOR | 4 | 3 | 5 | 3 |
| XNOR | 5 | 4 | 4 | 3 |
What the XOR gate does
An XOR gate outputs 1 when an odd number of its inputs is 1. For two inputs that is the same as “exactly one input is 1”.
Algebraically it is F = A ⊕ B, which expands to F = A′ · B + A · B′ = (A + B) · (A · B)′ = (A + B) · (A′ + B′). For n inputs, F = A₁ ⊕ A₂ ⊕ … ⊕ Aₙ — 1 when an odd number of inputs is 1.
- Commutative. A ⊕ B = B ⊕ A
- Associative. (A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) — unlike NAND and NOR, so a 3-input XOR cascade is well defined.
- Identity. A ⊕ 0 = A
- Controlled inverter. A ⊕ 1 = A′
- Self-cancelling. A ⊕ A = 0, A ⊕ A′ = 1, and A ⊕ B ⊕ B = A
- Bubble pair. A ⊕ B = A′ ⊕ B′ — two input bubbles cancel.
- Complement. (A ⊕ B)′ = A ⊙ B = A′ ⊕ B
XOR gate truth table
| k | A | B | F |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 2 | 1 | 0 | 1 |
| 3 | 1 | 1 | 0 |
| k | A | B | C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 | 1 |
| 5 | 1 | 0 | 1 | 0 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 1 |
| k | A | B | C | D | F |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 |
| 2 | 0 | 0 | 1 | 0 | 1 |
| 3 | 0 | 0 | 1 | 1 | 0 |
| 4 | 0 | 1 | 0 | 0 | 1 |
| 5 | 0 | 1 | 0 | 1 | 0 |
| 6 | 0 | 1 | 1 | 0 | 0 |
| 7 | 0 | 1 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 | 1 |
| 9 | 1 | 0 | 0 | 1 | 0 |
| 10 | 1 | 0 | 1 | 0 | 0 |
| 11 | 1 | 0 | 1 | 1 | 1 |
| 12 | 1 | 1 | 0 | 0 | 0 |
| 13 | 1 | 1 | 0 | 1 | 1 |
| 14 | 1 | 1 | 1 | 0 | 1 |
| 15 | 1 | 1 | 1 | 1 | 0 |
Boolean expression and canonical forms
At 2 inputs the function is F = A ⊕ B, with Σm(1, 2) and ΠM(0, 3). Expanded to canonical form that is F = A′ · B + A · B′ as a sum of products and F = (A + B) · (A′ + B′) as a product of sums.
Canonical form is unique once the variable order is fixed; minimal form is not. The minterm list is the shortest complete statement of the function and is what the Karnaugh map solver and the Quine–McCluskey solver both start from.
XOR gate symbol
Distinctive shape — ANSI/IEEE Std 91-1984
The distinctive-shape set draws the function as a body shape: a flat back with a semicircular nose is AND, a curved back with a pointed nose is OR, a triangle is a buffer, and an extra concave arc behind an OR body is XOR. A bubble on the output inverts the function; a bubble on an input inverts that input before the function is applied; two bubbles on one wire cancel.
The published proportions fix the AND, OR, XOR and bubble geometry but not the apex ratio of the buffer and inverter triangle. We use an apex 19 units from the base so the triangle matches the AND body width on the same sheet; the equilateral alternative, 13√3 ≈ 22.52, is equally defensible.
Rectangular shape — IEC 60617-12 (constructed metrics)
The rectangular set draws every gate as the same rectangle and puts a qualifying symbol in it: & for AND, ≥1 for OR, =1 for two-input exclusive-OR, 1 for a buffer or inverter. Negation is a circle tangent to the outline. Because every body is the same shape, the qualifying symbol is the whole of the information.
De Morgan equivalent symbol
A ⊕ B = A′ ⊕ B′
An XOR body with bubbles on both inputs — they cancel. A bubble on one input, or on the output, turns it into an XNOR.
IEC 60617-12:1997 is a paid standard and its per-symbol dimensions are not public. These rectangular symbols follow the published module-grid construction (module M = 6.5 units, so 4M = 26 matches the IEEE body height; line width M/10; qualifying symbol top-centre; connection pitch 2M; negation circle radius M/2 tangent outside the outline). The shapes and qualifying symbols are standard; the exact metrics are our construction, not a quotation.
Circuit description
Logic gate schematic. 2 inputs: A and B. 3 gates: 2 NOT and 1 XOR. The output F is driven by an XOR gate. The longest signal path passes through 2 gates.
Matching a bubbled output to a bubbled input lets a reader cancel the pair by eye and read the circuit’s intent, which is why the equivalent symbol is worth drawing at all.
Building a XOR gate from NAND gates only
n1 = NAND(A, B)= A ↑ Bn2 = NAND(A, n1)= A ↑ (A ↑ B)n3 = NAND(B, n1)= B ↑ (A ↑ B)n4 = NAND(n2, n3)= A ↑ (A ↑ B) ↑ (B ↑ (A ↑ B))
4 NANDs3 levels4 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Building a XOR gate from NOR gates only
n1 = NOR(A, B)= A ↓ Bn2 = NOR(A, A)= A ↓ An3 = NOR(B, B)= B ↓ Bn4 = NOR(n2, n3)= A ↓ A ↓ (B ↓ B)n5 = NOR(n1, n4)= A ↓ B ↓ (A ↓ A ↓ (B ↓ B))
5 NORs3 levels5 gates, 3 levels. Verified equivalent to the gate over all 4 input combinations.
Where the XOR gate is used
XOR is the most useful gate on this list. The half-adder sum is S = A ⊕ B with carry C = A · B. A chain of XORs over n bits is 1 when the number of 1s is odd, which is how a parity bit and a Hamming syndrome are computed. A ⊕ B is the “not equal” signal, so a bank of XORs OR-ed together compares two words. A ⊕ CTRL passes A when CTRL = 0 and inverts it when CTRL = 1, which is how a ripple-carry adder is turned into a subtractor. Binary converts to Gray code with Gᵢ = Bᵢ₊₁ ⊕ Bᵢ. LFSRs and CRCs are built from XOR taps. And because A ⊕ K ⊕ K = A, XOR is the operation behind the one-time pad and the three-XOR register swap. Standard part: 74HC86.
Gates people confuse with the XOR gate
XOR and OR
they differ on exactly one row, m₃ (11): OR gives 1, XOR gives 0. The English word “or” is usually exclusive; the gate called OR is inclusive. They differ on row m3 of the two-input table.
XOR and XNOR
exact complement on every row. XOR is the inequality function and XNOR is the equality function. They differ on rows m0, m1, m2, m3 of the two-input table.
XOR and NAND
XOR is 0,1,1,0 and NAND is 1,1,1,0, so they differ on exactly one row, m₀. Both are 1 when exactly one input is high. They differ on row m0 of the two-input table.
Common mistakes
- ✗ Writing A ⊕ B = A + B because A and B are never both 1 in this circuit.✓ True in that special case, but the gates differ in general. Write ⊕ if you mean exclusive.
- ✗ Treating a 3-input XOR as “exactly one input high”.✓ It is odd parity: 111 gives 1. “Exactly one” is the IEC =1 element, whose qualifying symbol for odd parity is 2k+1.
- ✗ Expanding A ⊕ B into A′B + AB′ and calling that the simplified answer.✓ Two literals beat four. The simplifier re-detects A′B + AB′ and returns A ⊕ B.
Start from a worked example
Worked examples
- A = 1, B = 1introthe row that separates XOR from OR
- Full 2-input truth tableintrotrue when the inputs differ
- 3-input XOR, A = 1, B = 1, C = 1coreodd parity, not exactly-one
- A ⊕ 0 and A ⊕ 1coreXOR as a programmable inverter
- Bitwise XOR: 1011 0110 ^ 0110 1101coredifference mask between two bytes
- XOR from four NAND gatesexamthe standard universal construction
- XOR expanded to SOPexamwhy XOR resists minimisation
- 4-bit equality comparator from XOR gatesedge caseXOR trees as comparators
Sources
- G. Boole, An Investigation of the Laws of Thought, Walton and Maberly, London, 1854.
- C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Transactions of the AIEE, vol. 57, pp. 713–723, 1938.
- A. De Morgan, Formal Logic: or, The Calculus of Inference, Necessary and Probable, Taylor and Walton, London, 1847.
- ANSI/IEEE Std 91-1984 with IEEE Std 91a-1991, IEEE Standard Graphic Symbols for Logic Functions.
- IEC 60617-12:1997, Graphical symbols for diagrams — Part 12: Binary logic elements. (Paid standard; see the construction note beside every rectangular symbol.)
- F. Gray, “Pulse Code Communication,” U.S. Patent 2,632,058, filed 13 November 1947, granted 17 March 1953 — the reflected binary code built from XOR.