Overflow: 100 + 100 in 8-bit signed — two's complement
corecarry out is not overflow
Answer
11001000
Why this example is worth doing
Two positive numbers whose sum exceeds +127 produce a negative result. The page states the detection rule precisely: signed overflow occurred when the carry into the sign bit differs from the carry out of it, which is not the same as the carry out being 1. Conflating carry and overflow is the classic error, and processors keep them as two separate status flags for exactly this reason.
Try your own input in the Two’s complement. Encode and decode signed binary at any width, with overflow and sign extension.
How the answer is reached
01100100 + 01100100 (8-bit, two's complement)
| operand | bits | hex | unsigned | signed |
|---|---|---|---|---|
| A | 01100100 | 0x64 | 100 | 100 |
| B | 01100100 | 0x64 | 100 | 100 |
| row | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| carry in | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| A | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
| + B | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
| result | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
C = 0 · V = 1 · N = 1 · Z = 0
unsigned100 + 100 = 200, kept as 200— fits in the width
signed100 + 100 = 200, kept as -56— V = 1: the signed answer is wrong
C is carry-out (unsigned overflow); V is carry-into-MSB XOR carry-out-of-MSB (signed overflow). They are independent: either, both or neither can be set.